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Observer
Observer
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Registered: ‎07-16-2019

MIPI CSI-2 Rx - Frame synchronization error

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Hi,

I have a duallane CSI Rx setup on an Ultrascale with Vivado 2019.1.1. I can succesfully receive frames from the camera via VDMA but the CSI interrupt status register shows a Frame synchronization error for VC0 (ErrFrameSync, Asserted when a FE is not paired with a FS on the same virtual channel PG232).

If the signal is captured with the scope it can be seen that on both data lanes the termination only for the Frame End packet is not working. This -1.2V peak can be seen for the Frame Start and each row of the transferred image but for the Frame End it is missing, which is highlighted in the scope images.

Differential measurement:

frameEnd_differential.png

SingleEnded: 

frameEnd_singleEnded.png

CSI registers after receiving one frame:

Core Configuration Register : 0x1
Protocol Configuration Register : 0x9
Core Status Register : 0x1580000
Global Interrupt Register : 0x1
Interrupt Status Register : 0x20002
Interrupt Enable Register : 0x0
Generic Short Packet Register : 0x0
VCx Frame Error Register : 0x0
Clock Lane Info Register : 0x2
Lane 0 Info Register : 0x0
Lane 1 Info Register : 0x0
Lane 2 Info Register : 0x0
Lane 3 Info Register : 0x0
Virtual Channel 0 Image Information 1 Register : 0x15802a0
Virtual Channel 0 Image Information 2 Register : 0x2c
Virtual Channel 1 Image Information 1 Register : 0x0
Virtual Channel 1 Image Information 2 Register : 0x0
Virtual Channel 2 Image Information 1 Register : 0x0
Virtual Channel 2 Image Information 2 Register : 0x0
Virtual Channel 3 Image Information 1 Register : 0x0
Virtual Channel 3 Image Information 2 Register : 0x0
Virtual Channel 4 Image Information 1 Register : 0x0
Virtual Channel 4 Image Information 2 Register : 0x0
Virtual Channel 5 Image Information 1 Register : 0x0
Virtual Channel 5 Image Information 2 Register : 0x0
Virtual Channel 6 Image Information 1 Register : 0x0
Virtual Channel 6 Image Information 2 Register : 0x0
Virtual Channel 7 Image Information 1 Register : 0x0
Virtual Channel 7 Image Information 2 Register : 0x0
Virtual Channel 8 Image Information 1 Register : 0x0
Virtual Channel 8 Image Information 2 Register : 0x0
Virtual Channel 9 Image Information 1 Register : 0x0
Virtual Channel 9 Image Information 2 Register : 0x0
Virtual Channel 10 Image Information 1 Register : 0x0
Virtual Channel 10 Image Information 2 Register : 0x0
Virtual Channel 11 Image Information 1 Register : 0x0
Virtual Channel 11 Image Information 2 Register : 0x0
Virtual Channel 12 Image Information 1 Register : 0x0
Virtual Channel 12 Image Information 2 Register : 0x0
Virtual Channel 13 Image Information 1 Register : 0x0
Virtual Channel 13 Image Information 2 Register : 0x0
Virtual Channel 14 Image Information 1 Register : 0x0
Virtual Channel 14 Image Information 2 Register : 0x0
Virtual Channel 15 Image Information 1 Register : 0x0
Virtual Channel 15 Image Information 2 Register : 0x0
Control Register : 0x2
IDelay Tap per lane for Rx Register: 0x0
Initialization Timer Register : 0x186a0
Wakeup Timer for ULPS exit Register : 0x0
Watchdog timeout in HS mode Register : 0x0
Goto Stop state on timeout timer Register : 0x0
Clk lane PHY error Status Register : 0x18
Data lane 0 PHY error Status Register : 0x15a0048
Data lane 1 PHY error Status Register : 0x15a0048
Data lane 2 PHY error Status Register : 0x8
Data lane 3 PHY error Status Register : 0x8
HS Settle Register L0: 0x91
IDelay Tap per lane for Rx 4-7 Register: 0x0
HS Settle Register L1: 0x91
HS Settle Register L2: 0x91
HS Settle Register L3: 0x91
HS Settle Register L4: 0x91
HS Settle Register L5: 0x91
HS Settle Register L6: 0x91
HS Settle Register L7: 0x91
Data lane 0 PHY error Status Register : 0x8
Data lane 1 PHY error Status Register : 0x8
Data lane 2 PHY error Status Register : 0x8
Data lane 3 PHY error Status Register : 0x8

On the hardware we also have the old image capturing solution with an Toshiba CSI Converter inbetween the camera and the FPGA with a Video In to AXI4-Stream core and there the Frame End is looking good. Therefore, I think it has to do something with the HW design.

Do you have any further ideas what can causing this behaviour?

 

Thanks and regards.

 

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Highlighted
Observer
Observer
73 Views
Registered: ‎07-16-2019

Hi, 

the issue is not seen on scope and CSI registers if the camera is directly connected instead with coaxial cables (10cm). 

So, I guess that the condition in the CSI IP is worsly received with the coax cables and because of the shorter time between last row and frame end, the incorrect termination can be only seen at frame end.

Thanks and regards.

View solution in original post

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Highlighted
Observer
Observer
74 Views
Registered: ‎07-16-2019

Hi, 

the issue is not seen on scope and CSI registers if the camera is directly connected instead with coaxial cables (10cm). 

So, I guess that the condition in the CSI IP is worsly received with the coax cables and because of the shorter time between last row and frame end, the incorrect termination can be only seen at frame end.

Thanks and regards.

View solution in original post