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Explorer
Explorer
1,122 Views
Registered: ‎09-25-2017

MIPI CSI-2 Rx SS 300MHz IDELAYCTRL clk critical warning when sharing bank

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Setup:

  Kintex 7 Speed grade 3

  Vivado 18.3

  MIPI Line Rate: 1500 Mbps

 

  I have 2 MIPI CSI-2 RX Subsys in a single HP bank.  Both MIPI need to input at 1500MBps but from different sensors.  I configured:

    1st MIPI IP

      "Include IDELAYCTRL in core" = TRUE

      "Enable 300 MHz clock for IDELAYCTRL" = TRUE

    2nd MIPI IP

      "Include IDELAYCTRL in core" = FALSE

      "Enable 300 MHz clock for IDELAYCTRL"  does not appear

For the 2nd IP, clk_300m input does not appear.

 

The design passes "Generate bitstream".  But I get critical warning:

  • [Timing 38-469] The REFCLK pin of IDELAYCTRL bd_i/mipi_0/inst/phy/inst/inst/bd_16a5_phy_0_rx_support_i/slave_rx.bd_16a5_phy_0_rx_phy_i/gen_idlyctrl_core.delayctrl has a clock period of 3.333 ns (frequency 300.030 Mhz) but IDELAYE2 bd_i/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d664_phy_0_rx_support_i/slave_rx.bd_d664_phy_0_rx_phy_i/mipi_dphy_v4_1_2_rx0_inst/idelay_cm has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.

Will this cause any problem?  Is there a walkaround if it does?

 

Regards,

Neo

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Xilinx Employee
Xilinx Employee
410 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

Adding some inputs from our internal communication to this thread, so other users can refer:

Will the critical warning cause any problem functionally?  That is, If we continue to run at 300MHz for test case, will the MIPI core work properly?

  • Yes, the Critical Warning will cause functional issues. MIPI Core will not work properly in this case.

Is there any action I can take (changing properties, modifying IP cores), along any of the phases ( design input, synthesis, implementation) that can configure the MIPI core to accept 300MHz so that warning is not generated?

  • No, there is no way that it can be bypassed.

Note: IP is tested for 1250 Mbps Max line rate, 1500 Mbps is not guaranteed by IP(Eventhough the customer can generate the IP at this line rate) as it depends upon different user settings & circuit used.

We recommend to continue to test your design with 200Mhz.

Regards,
Bhushan

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10 Replies
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Xilinx Employee
Xilinx Employee
1,103 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

Which Calibration mode you are using?

Please share your xci of your IP.

Please check following notes from PG232 carefully:

IDELAY1.jpg

 

IDELAY2.jpg

Please let us know your end goal and application details.

Regards,
Bhushan

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Explorer
Explorer
1,079 Views
Registered: ‎09-25-2017

Hi Bhusan,

  My settings:

    MIPI 0

      "Include IDELAYCTRL in core" = true

      "IODELAY_GROUP Name" = mipi_idly_group_0

      "Calibration mode" = AUTO

      "Enable 300 MHz clock for IDELAYCTRL" = true

 

    MIPI 1

      "Include IDELAYCTRL in core" = false

      "IODELAY_GROUP Name" = mipi_idly_group_0

      "Calibration mode" = AUTO

      "Enable 300 MHz clock for IDELAYCTRL" = unable to select once "Include IDELAYCTRL in core" = false

 

Finally I have connected MIPI 0 output port dlyctrl_rdy_out to MIPI 1 input port dlyctrl_rdy_in.

My setup have met all the conditions you highlighted.

 

I tried to attach XCI file but got these error messages when I post reply:


The attachment's bd_mipi_csi2_rx_subsyst_0_0.xci content type (application/octet-stream) does not match its file extension and has been removed.
The attachment's bd_mipi_csi2_rx_subsyst_0_1.xci content type (application/octet-stream) does not match its file extension and has been removed.

So I change extension to TXT, zipped and attached.

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Xilinx Employee
Xilinx Employee
1,061 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

Your MIPI CSI-2 RX IP settings seems to be correct.

Is it possible for you to provide test case design for reproducing this issue at our end?

or Share block diagram and constraints of your test case design?

Regards,
Bhushan

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Highlighted
Explorer
Explorer
1,045 Views
Registered: ‎09-25-2017

Hi,

  I have create a simple project that exhibits the same warning.  I have attached tcl file to recreate project in Vivado 18.3.

  The warning I am seeing is:

[Timing 38-469] The REFCLK pin of IDELAYCTRL bd_i/mipi_0/inst/phy/inst/inst/bd_5048_phy_0_rx_support_i/slave_rx.bd_5048_phy_0_rx_phy_i/gen_idlyctrl_core.delayctrl has a clock period of 3.333 ns (frequency 300.030 Mhz) but IDELAYE2 bd_i/mipi_1/inst/phy/inst/inst/bd_9019_phy_0_rx_support_i/slave_rx.bd_9019_phy_0_rx_phy_i/mipi_dphy_v4_1_2_rx0_inst/loop0[3].idelay_s has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.

 

Pls advise will this warning cause malfunction in MIPI core, OR the delay tuning is not affected by this warning.

Pls advise if I can use 200MHz ref clk for IDELAYCTRL when MIPI datarate is 1500Mbps, and it will work just fine.

 

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Xilinx Employee
Xilinx Employee
1,027 Views
Registered: ‎03-30-2016

Hello wtneo@leica 

Please use 200MHz clock for IDELAYCTRL , It will working just fine.

Thank you,

Leo

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Xilinx Employee
Xilinx Employee
1,019 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

I tried to run your demo tcl file with Vivado 2018.3 but it failed with error:

ERROR: [Vivado 12-172] File or Directory 'C:/v183_k7_demo/v183_k7_demo.srcs/sources_1/bd/bd/hdl/bd_wrapper.v' does not exist

Regards,
Bhushan

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Explorer
Explorer
1,006 Views
Registered: ‎09-25-2017

Hi Bhushan,

  Hmm I thought the TCL script will regenerate that automatically.

  So here it is.

 

 

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Explorer
Explorer
1,005 Views
Registered: ‎09-25-2017

Hi Leo,

  Ok tks.  Meanwhile I will try to see if any way to get 300MHz to work.

 

Neo

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Xilinx Employee
Xilinx Employee
552 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

I have downloaded bd_wrapper.v file. After running TCL script, now I am getting issue for top.xdc file missing.

I believe this source(s) files (bd_wrapper.v and top.xdc) were local or imported into the original project, so they were missing.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Highlighted
Xilinx Employee
Xilinx Employee
411 Views
Registered: ‎03-07-2018

Hello wtneo@leica 

Adding some inputs from our internal communication to this thread, so other users can refer:

Will the critical warning cause any problem functionally?  That is, If we continue to run at 300MHz for test case, will the MIPI core work properly?

  • Yes, the Critical Warning will cause functional issues. MIPI Core will not work properly in this case.

Is there any action I can take (changing properties, modifying IP cores), along any of the phases ( design input, synthesis, implementation) that can configure the MIPI core to accept 300MHz so that warning is not generated?

  • No, there is no way that it can be bypassed.

Note: IP is tested for 1250 Mbps Max line rate, 1500 Mbps is not guaranteed by IP(Eventhough the customer can generate the IP at this line rate) as it depends upon different user settings & circuit used.

We recommend to continue to test your design with 200Mhz.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------

View solution in original post