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Participant
Participant
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Registered: ‎11-05-2020

MIPI CSI-2 Rx Subsystem - Register Interface Configiration

I wanted to Know how Register Interface are Configured on a fly in MIPI CSI-2 Rx Subsystem through ARM.Can anyone please provide the solution for this as I am very new to this

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @Gangadhara 

You can take a look at MIPI Example Design mentioned in PG232 Chapter 5 for a reference.
MIPI CSI-2 RX Subsystem register interface is AXI4-lite interface, so you can use AXI interconnect IP to connect PS and MIPI CSI-2 RX SS.
PG232_Example_Design.png

Thanks & regards
Leo

Participant
Participant
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Registered: ‎11-05-2020

thanks for your Interest!

I refered example design of RX SS,I got to know through AXI-4 interface it is configured.
What i would like to understand is how is rx subsystem configured on Vitis.
For example to enable soft reset, how should it be programmed on vitis
 
Also, are the driver details for RX subsystem register interface available for example design?
It would be helpful if you could name the source code that should be refered to.

 

Your help will be appreciated

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @Gangadhara 

Details can be found in PG232 Chapter 5.
0. After you have built your MIPI CSI-2 RX Example Design, export hardware (XSA file).
1. Open your Vitis IDE, select "Board Support Package" for psu_cortex53_0.
2. On the Drivers list, select "mipicsiss"
3. Click on "Import Examples" to import example source codes.

mipicsiss.png

Thanks & regards
Leo

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Participant
Participant
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Registered: ‎11-05-2020

I have designed the tx subsytem which is driven from the vtpg module , I have build the design and exported accordingly.

after launching the vitis and selecting BSP in that driver section mipi_csi2_tx_subsyst_0 I couldnt find import example for that. Can you please provide the solution for it

down we have picture of that

tx bsp pic.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @Gangadhara 

Unfortunately, Only MIPI CSI-2 RX application driver "mipicsiss" supports "Import Examples".
I shall give internal teams feedback to add "Import Examples" feature for MIPI CSI-2 TX too.

For now, please add source from the following folder manually.
    {XILINX}/Vitis/2020.1/data/embeddedsw/XilinxProcessorIPLib/drivers/csi2txss_v1_3/

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
426 Views
Registered: ‎03-30-2016

Hello @Gangadhara 

Currently, We don't have any plan to create MIPI CSI-2 TX Subsystem example application.
So, "Import Example" will not available in Vitis Drivers list.

Thanks & regards
Leo

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Participant
Participant
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Registered: ‎11-05-2020

thanks for your interest , but I wanted to know how to program the tx subsystem in my design on vitis?, like how to read the configuration register and enable the core

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @Gangadhara 

Xilinx provided a standard IO Interfacing APIs in xil_io.h, functions such as Xil_In32 and Xil_Out32 can be used for this purpose.
xil_io.h.png

Please see also the following document :
    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/oslib_rm.pdf

Usage example :
    data = Xil_In32( addr )
    Xil_Out32( addr, data )

Regards
Leo

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Participant
Participant
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Registered: ‎11-05-2020

Thanks for your Interest,

In the Mentioned folder "{XILINX}/Vitis/2020.1/data/embeddedsw/XilinxProcessorIPLib/drivers/csi2txss_v1_3/"  in the example folder I gone through the Interupt C file where they have used the Function call for Enabling the Core [Xcsi2TxSs_Activate(&Csi2TxSsInst, xCsI2tx_Enable)] I didn't find the Function definition for it.

Is there anyway i can find it(like reading the TX register and changing a particular bit to enable the TX core).

It will be very helpful for us as I am on hold for this for a long time

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Adventurer
Adventurer
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Registered: ‎09-05-2020

I don't know anything about mipi, but the axilite interface is very simple. The Vivado address editor will list the base address of the ip and the ip data sheet will list all the registers with bit definitions and address offsets. That's all you need to know to write/read the registers in the ip. I use volatile uint32 pointers, easy peasy.

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Participant
Participant
187 Views
Registered: ‎11-05-2020

 what will be the format of read out value while using Xil_In32 function?, it will be in hex,oct,bin,decimal?

 

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Xilinx Employee
Xilinx Employee
160 Views
Registered: ‎03-30-2016

Hello @Gangadhara 

The data type is 32bit unsigned integer (u32) data type. You can displayed as Hex, Dec, Bin whatever you prefer. 

   RegisterAddress = BASEADDR + 0x0;
   RegisterValue = Xil_In32(RegisterAddress);
   xil_printf("Register Value is : %x\n\r", RegisterValue);

Regards
Leo

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