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okgultekin_44
Observer
Observer
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Registered: ‎01-15-2019

MIPI CSI-2 TX Configuration

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Hello everyone,

 

I'm trying to use csi-2 tx subsytem in my design. As a input video source, I am using Video Test Pattern Generator.

 

Firstly I am configuring TPG IP.

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0010 ,0x2D0 // Height 720

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0018 ,0x438 // Width 1080

..

..

bla bla bla (background fforeground patterns, mask id, motion speed... etc)

...

..

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0040, 0x0 // Color Format RGB

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0098, 0x1 // Enabled Input

..

..

bla bla (pass throught Start/End X Y, dynamic range. .. etc)

..

..

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0000, 0x80 // Restart TPG

XPAR_V_TPG_S_AXI_CTRL_BASEADDR + 0x0000, 0x01 // Start TPG

 

CSI-2 TX subsytem configuration comes after TPG configuration.

Disable Interruption

Controller is ready

Enable soft reset

Disable soft reset

Set 4 Lanes

Enable Global Interruption

Enable the core

SP DataType 0x24 RGB888

 

And also I added ILA cores to monitor axis video stream signals between TPG and CSI-2 TX cores. 

 

Capture.PNG

 

To start video transmission, TUSER signal should be logic high but newer rise to high state. 

Is there any problem about my configuration? 

And is there any reference design and axi stream code about csi-2 tx 

 

 

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1 Solution

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karnanl
Xilinx Employee
Xilinx Employee
1,103 Views
Registered: ‎03-30-2016

Hello @okgultekin_44 

Unfortunately, you have to install Vivado 2019.1, and generate the example design yourself.

Just for your reference, attached testbench RTL file generated from 2019.1.
I believe you can use it with 2018.3 simulation too, but I've never try the simulation myself. : -)

Please note:

# Xilinx only provided two configuration CSI-2 TX IP for simulation.
# We cannot run the example design simulation usinh only this single testbench RTL.

Thanks & regards
Leo


------------------------------------------------------------------------------------------------
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6 Replies
karnanl
Xilinx Employee
Xilinx Employee
1,172 Views
Registered: ‎03-30-2016

Hello @okgultekin_44 

 

Please try to run MIPI CSI-2 TX Subsystem Example design simulation. It is a good start point.

We provided 2 Example Design configuration

   A) 1 Lane RGB888 1 Pixel Mode

   B) 4 Lane YUV422 4 Pixel Mode

Both configuration using AXI4 stream I/F. See also PG260 Chapter 5. (https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_0/pg260-mipi-csi2-tx.pdf)

 

Looking at your ILA waveform, it seems that TUSER is never asserted.

Perhaps doing some simulation , before HW verifications will help.

 

Regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
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okgultekin_44
Observer
Observer
1,139 Views
Registered: ‎01-15-2019

@karnanl  thank you for your reply.

 

Unfortunately, I couldnt find any example design. 

When I right click on mipi csi2 tx subsystem IP, I counldnt find any example design.

Capture1.PNG

 

Capture.PNG

 

karnanl
Xilinx Employee
Xilinx Employee
1,127 Views
Registered: ‎03-30-2016

Hello @okgultekin_44 

What is your Vivado version ? Example Design is available in 2019.1 IP.

Please see also IP change log :
2019.1:
* Version 2.0 (Rev. 5)
* New Feature: Added example design
* Revision change in one or more subcores


Thanks
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
okgultekin_44
Observer
Observer
1,121 Views
Registered: ‎01-15-2019

Hello @karnanl,

 

Im using old version of vivado (18.3) 

Is there any way to get example design without upgrade vivado? maybe a link or github? 

 

Thx for your help

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karnanl
Xilinx Employee
Xilinx Employee
1,104 Views
Registered: ‎03-30-2016

Hello @okgultekin_44 

Unfortunately, you have to install Vivado 2019.1, and generate the example design yourself.

Just for your reference, attached testbench RTL file generated from 2019.1.
I believe you can use it with 2018.3 simulation too, but I've never try the simulation myself. : -)

Please note:

# Xilinx only provided two configuration CSI-2 TX IP for simulation.
# We cannot run the example design simulation usinh only this single testbench RTL.

Thanks & regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

okgultekin_44
Observer
Observer
1,090 Views
Registered: ‎01-15-2019

thank you @karnanl  !