cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
msattine
Contributor
Contributor
703 Views
Registered: ‎11-27-2018

MIPI CSI-2 TX Configuration

Jump to solution

Hi,

My design is having an AXI4-stream which is of data width 64 bits. These 64 bits correspond to 4 channels, each channel being 16-bit wide.

I am trying to figure on how to configure MIPI CSI2 TX subsystem so that it takes in the above AXI4-stream in RAW8 format.

The data width observed with pixels per beat set to 1 is 48-bits. Documentation says that the width is 14*3*(pixel mode). What are the numbers 14 and 3 correspond to? It is not mentioned anywhere in the product guide.

Any help here is appreciated.

-

Mohan

 

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
karnanl
Xilinx Employee
Xilinx Employee
613 Views
Registered: ‎03-30-2016

Hello Mohan @msattine 

Could you please check the following doccument ?
https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_1/pg260-mipi-csi2-tx.pdf

You should assign RAW8 data input as follow :
Mohan_Pixel_bit_assignment.png

Other than Data Type and Frame Start, you also need to set the correct Word Count,
You may set Line/Frame number as a fixed zero if your receiver does not need this information.

Mohan_tuser.png

Thanks
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

3 Replies
karnanl
Xilinx Employee
Xilinx Employee
631 Views
Registered: ‎03-30-2016

Hello Mohan @msattine 

PG260 mentioned that : Data Width = Byte aligned of (14*3*Pixel Mode)

So if
Pixel Mode =1 --> s_axis_tdata = 14x3x1 = 42. CEIL(42,8)=48
Pixel Mode =2 --> s_axis_tdata = 14x3x2 = 84. CEIL(84,8)=88
Pixel Mode =4 --> s_axis_tdata = 14x3x4 = 168.

This is due to IP requirement to accept 3 colors/component at the same time(RGB888, YUV422) and RAW14 data type.
Bitwidth is redudant to make the data bit assignment systematic and easy to use.

Regards
Leo

Pixel Mode.png


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
msattine
Contributor
Contributor
621 Views
Registered: ‎11-27-2018

Hi Leo, 

Thanks for the quick response.

So for my case is this how I should drive the AXIS? (With pixels per beat = 4 and RAW8 data type)

--------------------------------------------------------------

s_axis_tdata[167:0] = {112'b0, video_data[31:24], 6'b0, video_data[23:16], 6'b0, video_data[15:8], 6'b0, video_data[7:0], 6'b0};

s_axis_tuser[0] = start_of_frame; // aligns with first pixel of first line

s_axis_tuser[6:1] = 6'h2A; // RAW8 data type

--------------------------------------------------------------

Is this sufficient or do I also have to drive other fields of tuser? What will happen if I dont drive other fields in truser?

-

Mohan.

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
614 Views
Registered: ‎03-30-2016

Hello Mohan @msattine 

Could you please check the following doccument ?
https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_1/pg260-mipi-csi2-tx.pdf

You should assign RAW8 data input as follow :
Mohan_Pixel_bit_assignment.png

Other than Data Type and Frame Start, you also need to set the correct Word Count,
You may set Line/Frame number as a fixed zero if your receiver does not need this information.

Mohan_tuser.png

Thanks
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post