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Visitor
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Registered: ‎06-29-2020

MIPI CSI Rx immediately filling Stream Line Buffer and going to Stop State

I have a problem initiating video using the MIPI CSI Rx Subsytem. Having initialised and enabled the subsystem it immediately raises a Stream Line Buffer Full interrupt (Rx Controller Reg offset: 0x24, Interrupt Status Register = 0x20000) and enters a Stop State on the Clock and active data lanes. The associated DPHY core is intialised and has asserted the  ERR_CONTROL bit on the Clock Lane Status Register (offset 0x18, value 0x18) and ESC and HS timeout errors on the active Data Lanes (offsets 0x1C & 0x20, values 0x48).

I am using the MIPI CSI Rx Subsystem IP on Vivado 20.1.1 on the AC701 hardware platform and I am passing the converting the DPHY signals to LVDS/CMOS using the compliant solution from XAPP894. The sensor is an OV5640 running at 10bit RAW 720p60 with 2 CSI lanes and the CSI Rx includes the video format bridge streaming to a Test Pattern Generator in passthrough via 2-pixel per clock AXI-S at 100MHz. 

I'm aware that the the Stream Line Buffer full interrrupt indicates that the video data is not transmitting along the AXI-S fast enough, if at all, but I'm also not sure if the CSI Rx is starting up correctly because of the DPHY clock lane status assertion of the ERR_CONTROL bit. No packets have been counted by the DPHY, which may suggest it is related to this, but I don't understand why the result in the Rx Controller is the Stream Line Buffer Full interrupt.

Could you help me work out how I can further diagnose the problem here?

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Visitor
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Registered: ‎06-29-2020

Further to this:

After making a MIPI config change in the camera sensor the errors in the CSI controller registers are now limited to the Line Buffer Full interrupts. In this situation the Clock and Data lines are no longer in stop states and the DPHY core Data Lane status registers are at 0x9 values stating the lanes are in High Speed mode. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

MIPI CSI-2 RX
  Offset 0x24 = 0x20000 (STOP_STATE=1)
  -- I do not see any issue on those register dump

MIPI D-PHY RX
  Offset 0x18 = 0x18 (STOP_STATE=1, INIT_DONE=1)
  Offset 0x1C = 0x48 (STOP_STATE=1, INIT_DONE=1)
  Offset 0x20 = 0x48 (STOP_STATE=1, INIT_DONE=1)
  -- I do not see any issue on those register dump

Could you please explain what is the issue you have observed on your HW ?

Thanks & regards
Leo

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Visitor
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Registered: ‎06-29-2020

Hi Leo, 

Thanks for your reply. The problem I have is a failure of the RX subsystem to being receiving/streaming data when the CSI2 initialises. 

I am configuring the sensor and enabling the CSI2 but I cannot get the receiver to accept the initialisation. Here is the full register drop:

 RX Controller RegistersValue 
0x00Core Config0x1enabled
0x04Protocol Config0x92 active lanes
0x10Core Status0x0 
0x20Global Interrupt En0x1enabled
0x24Interrupt Status0x20000Stop State
0x28Interrupt Enable0xC07DFFFF 
0x30Generic Short Packet0x0 
0x34VCX Frame Error0x0 
0x3CClock Lane Info0x0 
0x40Lane0 Info0x2SoT Error
0x44Lane1 Info0x2SoT Error
0x48Lane2 Info0x0 
0x4CLane3 Info0x0 
 DPHY Core Registers  
0x0Control0x2enabled
0x4IDELAY_TAP_VALUE0x1010101 
0x8Init0x7A1200.5 msecs
0x10HS Timeout0x1000565,541
0x14 ESC Timeout0x640025,600
0x18Clock Lane Status0x8Init done. LP mode
0x1CLane0 Status0x48ESC Abort, Init Done
0x20Lane1 Status0x48ESC Abort, Init Done
0x24Lane2  Status0x8 
0x28Lane3 Status0x8 
0x30HS Settle reg0x94148ns
0x48HS Settle 10x94 
0x4CHS Settle 20x94 
0x50HS Settle 30x94 
0x54HS Settle 40x94 
0x58HS Settle 50x94 
0x5CHS Settle 60x94 
0x60HS Settle 70x94 
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

I can see that D-PHY packet counter is "0" and all clock/data lanes are in low-power mode, so perhaps MIPI D-PHY RX does not observed LP11-LP01-LP00 transition from your sensor.

1. Please share your MIPI CSI-2 RX XCI file. ( I need to check Vivado version and configuration )
2. Did you configure the line-rate setting to match sensor output line-rate ?
3. Could you please check your board for any unintentional P/N swap for both clock-lane and data-lanes ?
4. Do you have any oscilloscope waveform on clock-lane (P/N) and data-lane 0,1 (P/N) to share ?

BTW in your register dump , ESC Abort is not asserted.
REG_analysis.png

Thanks & regards
Leo

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Visitor
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Registered: ‎06-29-2020

Hello @karnanl 

The DPHY Lane Status Register and CSI Controller Lane Info Register are actually jumping in and out of 0x9/0x48 and 0x0/0x20 respectively so they appear to be recognising HS mode on some occasions. 

Below is an image of the LP11-LP01-LP00 transition on DL0 for a 360Mbps line rate, which is what the CSI Subsystem is configured as. 

RobLeigh_1-1603799415731.png

Thanks for pointing out my misreading of ESC_ABORT for STOP_STATE.

I've double-checked and I don't have the P/N swap issues. I am using a MC20901 as part of a Digilent FMC adapter board, which does have pin-swap enabled, but I've accounted for that

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Visitor
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Registered: ‎06-29-2020

@karnanl 

I can't get the forum to accept the .XCI for the mipi receiver subsystem. My vivado sw & ip build is show here though if that helps?

RobLeigh_0-1603801603039.png

 

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Visitor
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Registered: ‎06-29-2020

Hi @karnanl 

A bit of follow up to this. The Mipi Rx controller is intermittently picking up frames and data packets. Loading by scope probes on the Clock lanes makes this more likely, though there remains a Stop Error interrupt for each Frame Received interrupt I'm picking up. 

So it seems like there's a problem with entry/exit timings on the Clock lane although it's a bit inconsistent. I can manipulate the timings for this in the Mipi Tx in the camera sensor but I'm not sure how to determine the appropriate settings. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

1. Yes, I forgot to say that you need to zip XCI before attach it to your post.

2. "Athough there remains a Stop Error interrupt for each Frame Received interrupt I'm picking up. "

BTW, STOP_STATE is not an error. examples\xcsiss_intr_example.c need some modification.
Currently, CsiSs_ErrEventHandler is treating Stop-state as an error.
This is not correct. Stop-State is a normal state during MIPI CSI-2 data transmission (==LP-11 is observed at input pins)
I've reported this to software team, this should be fixed in 2020.2
For now please remove those lines from CsiSs_ErrEventHandler.
STOP_STATE_is_not_an_error_state.png

3. Did you set MIPI clock from sensor as Continuous mode (Free-running) or Non-continuous mode ?
    # You need to configure MIPI lines to send LP-11, when no packet to transmit.

Sensor_setting.png

Thanks & regards
Leo

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Visitor
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Registered: ‎06-29-2020

Hi @karnanl 

Thanks for your help with this. My MIPI Clk is free running. 

The problem it is presenting now is reported as a protocol level interrupt; packet level error ; Frame sync. It is picking up the Virtual Channel I configure the sensor to and reports the error against this VC.

Do you have any advice on adjustments to get round this?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

>Thanks for your help with this. My MIPI Clk is free running. 

Noted.

>The problem it is presenting now is reported as a protocol level interrupt; packet level error ; Frame sync. It is picking up the Virtual Channel I configure the sensor to and reports the error against this VC.


The latest register dump in your previous post showing ISR=0x2_0000 , means Stop_state=high.
Could you please share the latest register dump ( for both MIPI CSI-2 RX & MIPI D-PHY) , and please share your zipped XCI file.

Thanks
Leo

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Visitor
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Registered: ‎06-29-2020

Hi @karnanl 

Here are the registers and the zipped xci.

Not shown in the register dump are the error interrupts. When running I keep getting the VC Frame Sync error but at initialisation i get a single of each of the following interrupts:

SoT Sync Error, Word Count Corruption, SoT Error, 1 bit ECC Error

 RX Controller Registers
0x00Core Config0x1
0x04Protocol Config0x9
0x10Core Status0x97840000
0x20Global Interrupt En0x1
0x24Interrupt Status0x0
0x28Interrupt Enable0xC07FFFFF
0x30Generic Short Packet0x0
0x34VCX Frame Error0x0
0x3CClock Lane Info0x0
0x40Lane0 Info0x0
0x44Lane1 Info0x0
0x48Lane2 Info0x0
0x4CLane3 Info0x0
0x70VC2 Info 10x9BD9096A
0x74VC2 Info 20x2B
 DPHY Core Registers
0x0Control0x2B
0x4IDELAY_TAP_VALUE0x1010101
0x8Init0x7A120
0x10HS Timeout0x10005
0x14 ESC Timeout0x6400
0x18Clock Lane Status0x9
0x1CLane0 Status0xA1AA0009
0x20Lane1 Status0xA2760009
0x24Lane2  Status0x8
0x28Lane3 Status0x8
0x30HS Settle reg0x120
0x48 to 0x60HS Settle 1 to 70x120
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

1. Thank you for sharing your XCI.

    MIPI_ROB_720Mbps.png
    Noticed one thing.
    You said your sensor sends 360Mbps MIPI signal, but I found that MIPI CSI-2 RX is configured as 720Mbps.
    Please set line-rate to match your sensor output line-rate.

2.  (After you can confirmed that line-rate setting is correct)
    I also notice that ISR (offset 0x24) is all zero. So perhaps MIPI CSI-2 RX is not receiving Frame-End Short Packet.
    ( bit 31 should be asserted if MIPI CSI-2 RX received a valid Frame-End )

    Frame_received_flag.png
      In the other hand, MIPI D-PHY receives HS packet.
          MIPI_DPHY_PACKET_CNT.png
      So, could you please check :
          (a) whether you data lane0 and data_lane 1 is not swapped.
          (b) your sensor is sending Frame-End short packet ?

3. Could you please do experiment with GUI setting on your HW ?
    Please disable the following options :

   karnanl_0-1603963695290.png

 


Thanks & regards
Leo

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Visitor
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Registered: ‎06-29-2020

Hi @karnanl 

I sometimes slowed the line rate down to 360Mbps for testing and when I did this it was both on the camera and on the CSI Rx subsystem. I observed the same behaviour at both line rates.

A short packet is being transmitted in the centre of the blanking period, but I agree it seems to be missing this. Note that I have observed extremely occasional frame received interrupts from the CSI subsystem, which implies it is a timing or noise related issue. 

I've sanity checked the tracing and I'm certain the data lanes have not been swapped. 

Also I have disabled the CSI Spec V2_0 option in the GUI and continue to receive the Frame Sync Error

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Registered: ‎06-29-2020

Hi @karnanl  

Following up to this I thought the HS-Zero period on the Data Lanes was excessively long and when reducing that to 100-150ns the CSI Rx subsystem is now reporting frames being received.

I'm still getting an initial ECC error and a word count corruption error - if these are just once at transmission initialisation presumably they're of no consequence though?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @RobLeigh 

Thank you for your update.

>I sometimes slowed the line rate down to 360Mbps for testing and when I did this it was both on the camera and on the CSI Rx subsystem. I observed the same behaviour at both line rates.

Okay. I see no issue if MIPI CSI-2 RX line-rate setting is matching sensor output line-rate.

>1. I've sanity checked the tracing and I'm certain the data lanes have not been swapped.
>2. Also I have disabled the CSI Spec V2_0 option in the GUI and continue to receive the Frame Sync Error

Noted on both.

>A short packet is being transmitted in the centre of the blanking period, but I agree it seems to be missing this.
>Note that I have observed extremely occasional frame received interrupts from the CSI subsystem, which implies it is a timing or noise related issue.

I do agree, but I cannot comment on this since I don't see any detailed waveform data from your system.

>Following up to this I thought the HS-Zero period on the Data Lanes was excessively long and when reducing that to 100-150ns the CSI Rx subsystem is now reporting frames being received.

This is confused me a bit.
According to MIPI D-PHY spec, THS-PREPARE + THS-ZERO has minimum spec of (145ns+10UI), but no max value defined by the spec.
DPHY_spec_for_prep_HS_zero.png

>HS-Zero period on the Data Lanes was excessively

I am not clear with the actual THS-ZERO value on your system , but MIPI D-PHY RX IP has a watchdog implementation (HS_TIMEOUT parameter).
HS packet will be discarded if the packet is longer than expected.


>I'm still getting an initial ECC error and a word count corruption error - if these are just once at transmission initialisation presumably they're of no consequence though?

Would you able to clear MIPI CSI-2 RX ISR register ? You need to write "1" on each ISR bit to clear the error flag asserted.
Do it a few times, please let me know if you still see ECC error or WC corruption error.

Please let me know if my explanation above is not clear.

Thanks & regards
Leo

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