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Visitor
Visitor
1,757 Views
Registered: ‎06-11-2018

MIPI CSI TX throughput mismatch - simulation in Modelsim

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Hi,

We are performing the IP integration and netlist simulation of MIPI CSI Tx IP in modelsim after completing the simulation in Vivado. 

 

Problem : Xilinx recommends 20-30% higher input through put than output throuthput.(pg260-mipi-csi2-tx.pdf page 27) . But we are observing line buffer full interrupt from Tx, and data miss occurs. While keeping the same throughput no interrupt is observed. But on vivado simulation keeping 20% higher throughput does not trigger interrupt, same throughput triggers underrun interrupt. 

 

The configuration Parameters are :

Lane rate : 238 Mbps
Pixel mode: 1
Data type : RAW8
Image : 1280 x 720
Line buffer depth : 4096
Target : 7 series family

 

Can you please help us to find what is going wrong?

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Visitor
Visitor
1,254 Views
Registered: ‎05-14-2018

the EoL generation disabling solved my bandwidth problems with non continous mode, thanks for the suggestion

 

shyam

 

https://forums.xilinx.com/t5/Video/MIPI-CSI2-Tx-in-native-mode-and-non-continuous-clock/m-p/899483

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Xilinx Employee
Xilinx Employee
1,731 Views
Registered: ‎03-30-2016

Hello @jobincyriac

 

1. Could you please share your XCI file ?

2. What is your s_axis_aclk frequency ?

3. Are you using Native video interface ?

4. Are your Vivado simulation and Modelsim simulation using excatcly the same testbench (MIPI CSI-2TX has excatly the same input pattern ) ?

5. Could you show me the simulation waveform of MIPI CSI-2 TX input and MIPI D-PHY TX PPI I/F ?

 

Best regards

Leo

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Visitor
Visitor
1,707 Views
Registered: ‎06-11-2018

Hello @karnanl,

 

1. Will share you by mail

2. s_axi_clk : 74.25MHz

3.Yes, Native video interface is used.

4. No. We are using different testbenches, but keeping the stimulus same. (Current modelsim simulation is a full chip sim, vivado sim mipi csi alone.)

5. Will share the vcd file by mail.

 

Regards,

Jobin

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Xilinx Employee
Xilinx Employee
1,674 Views
Registered: ‎03-30-2016

Hello Jobin @jobincyriac

 

Thank you for sharing your XCI & VCD.

I just Looked at your VCD, here are my observation.

 

1. Your h-blanking time on Native video I/F is too short.

    I compared vid_enable & dl0_txreadyhs assertion timing. As you can see that the difference is getting bigger and bigger every line. You will have buffer overflow.

 

 vid_enable assertion timingdl0_txreadyhs assertion timingtiming
difference
LINE2171786317225414678
LINE3174005817469116853
LINE4176225417712659011
LINE51784449179566711218
All in [ns]   

 

2. Your current h-blanking is approx. 5000ns

    You need at least 7200 ns + margin to make line-buffer not overflowed.

 

3. If you cannot do that , I suggest you to turn off Line-Start/Line-end.

   I see that you are sending Line-Start/Line-end synchronization short packet.

   Line-Start/Line-end synchronization short packet is optional for MIPI CSI-2 protocol.

   If your RX do not need Line Start/end information ( or do not need line number information )

   suggest you to turn it off. It give you a margin for about 1000-1300ns on h-blanking.

 

4. your current s_axis_aclk should be fine.

 

Best regards

Leo

XF_JOBIN_WAVEFORM2.png
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Visitor
Visitor
1,655 Views
Registered: ‎06-11-2018

Hello @karnanl,

 

Thanks for your feedback. Will check your comments and get back with more details.

 

Jobin

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Moderator
Moderator
1,568 Views
Registered: ‎11-09-2015

Hi @jobincyriac,

 

Do you have any updates on this?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Highlighted
Visitor
Visitor
1,255 Views
Registered: ‎05-14-2018

the EoL generation disabling solved my bandwidth problems with non continous mode, thanks for the suggestion

 

shyam

 

https://forums.xilinx.com/t5/Video/MIPI-CSI2-Tx-in-native-mode-and-non-continuous-clock/m-p/899483

View solution in original post