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1,131 Views
Registered: ‎03-30-2017

MIPI CSI2 RX - does not assert interrupt

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Hi there,

We are using the MIPI CSI2 RX IP (evaluation license) to collect data from an external device.

At the moment, the IP doesn't assert the interrupt while it should be working.

Before entering into FPGA/FW details, we would like to be sure to have properly fed its input pins from the external device.

 

- According to XAPP894, we implemented an external network (unidirectional case) to convert signal from the external MIPI CSI TX to LVDS standard (400mVpp, Vref 1.2V);

- In the MIPI CSI2 RX IP we are using only input pins HS (clock HS and data line 0 HS, LP pins are not connected).

- The Zynq we are using is the 7030 series.

- The bit rate on the line is 150Mbps, the video clock in input to the IP is 100MHz.

 

Is this setup correct to properly drive the MIPI CSI2 IP input pins? Or do we need to do some other modifications to the hardware?.

If the setup works properly, I would expect some interrupt signal indicating that somethis is happening.

 

Thank you in advance for you help.

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Xilinx Employee
Xilinx Employee
1,081 Views
Registered: ‎03-30-2016

Hello @paolofalconearesys

 

- In the MIPI CSI2 RX IP we are using only input pins HS (clock HS and data line 0 HS, LP pins are not connected).

 

1. Your system will not work.

    You need to connect LP pins too, to make MIPI CSI-2 RX SS initialized sucessfully.

    MIPI specification mentioned that MIPI TX should drive serial lines to LP-11 for a period longer than INIT_TIME.

    If you are not connecting LP pins, Xilinx MIPI CSI-2 RX will not assert INIT_DONE register.

 

2. BTW, Do you have an access to MIPI D-PHY specification ver1.1 and MIPI CSI-2 specification ver1.1 from mipi.org ?

    If not please download the documents above.

 

 

Thanks & regards

Leo

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Xilinx Employee
Xilinx Employee
1,082 Views
Registered: ‎03-30-2016

Hello @paolofalconearesys

 

- In the MIPI CSI2 RX IP we are using only input pins HS (clock HS and data line 0 HS, LP pins are not connected).

 

1. Your system will not work.

    You need to connect LP pins too, to make MIPI CSI-2 RX SS initialized sucessfully.

    MIPI specification mentioned that MIPI TX should drive serial lines to LP-11 for a period longer than INIT_TIME.

    If you are not connecting LP pins, Xilinx MIPI CSI-2 RX will not assert INIT_DONE register.

 

2. BTW, Do you have an access to MIPI D-PHY specification ver1.1 and MIPI CSI-2 specification ver1.1 from mipi.org ?

    If not please download the documents above.

 

 

Thanks & regards

Leo

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Moderator
Moderator
1,038 Views
Registered: ‎11-09-2015

HI @paolofalconearesys,

 

Was @karnanl's reply enough for you?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
1,031 Views
Registered: ‎03-30-2017

I Florent,

The answer by karnanl was useful.

At the moment, we are facing the transmitter side with the master's manufacturer but we haven't still solved the issue.

 

Highlighted
Visitor
Visitor
914 Views
Registered: ‎07-26-2016

What are you saying is that in order for the MIPI CSI2 RX system to work all hs and lp lines must be connected?

This is my current design that I'm afraid It will not be compatible with the Xilinx IP.


Capture3.PNG

 Regards,

 

 

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Xilinx Employee
Xilinx Employee
901 Views
Registered: ‎03-30-2016
Hello @jnievesr,

Short answer : Yes LP lanes need to be connected.

Could you please post a new question in Video board for this topic?
Please share your system connectivity too. (What is TX(Sensor?) and RX (FPGA?) )

Thanks & regards
Leo
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