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gregbalke
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Registered: ‎04-08-2021

MIPI CSI2 RX - only receives first line

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Hi there!

I've got a system that looks like: MIPI PHY -> MIPI CSI2 RX Subsystem -> VDMA -> AXI_SMC -> Zynq Ultrascale+

gregbalke_0-1624391216158.png

I had a previous system set up on an enclustra development board that had this setup working just fine. Since then, we've designed a custom board and added some additional cameras. Now when I use the exact same configuration as before for each MIPI block, my DMA only sends the first burst of packets and then freezes. The software is identical and the hardware is still sending packets as can be seen by debugging just after the physical block in the subsystem: 

gregbalke_1-1624391414713.png

The first line or so of data is transmitted from the VDMA over AXI as seen here.

screenshot-2021-06-22_11_34_26.png

screenshot-2021-06-22_11_33_24.png

Now with the same sensor on the development system:

screenshot-2021-06-21_11_18_22.png

I noticed that the actual MIPI to VDMA AXI (the red line in the block diagram) will not trigger leading me to believe there is something wrong with the rx subsystem but I'm not sure where to start for the debug. I have a feeling it might be something to do with channel synchronization but the first individual lines are correct (change intensity when I vary light to the camera). This makes me believe something is going wrong where a system to reset to get the next line is not working correctly. To be more specific, I get the first 2 lines and this is a 2 channel system.

gregbalke_2-1624392161121.png

Any help would be greatly appreciated, thank you!

 

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gregbalke
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Registered: ‎04-08-2021

I traced through the entire signal path and discovered the signal just disappeared on the stretch between the video_out and S_AXIS_S2MM of the axi_vdma (the red connection). I ended up directly connecting the outputs/inputs and everything started working... Please report this to the developers as this consumed a huge amount of time and is damaging to my trust of the block diagram system.

gregbalke_0-1624474621451.png

To note: When I probed the synthesized output of the VFB (Video Format Bridge), it showed signals coming out so I believe the protocol is correct as RAW12. I noticed this issue is similar to @saiwing_hit's https://forums.xilinx.com/t5/Video-and-Audio/MIPI-CSI-2-RX-Subsystem-RGB565-format-settings/td-p/1254713 but ended with a different result.

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gregbalke
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Registered: ‎04-08-2021

I did some additional debug between the rx block and the vfb block. The RX block is actually outputting data continuously: 

screenshot-2021-06-22_14_08_21.png

screenshot-2021-06-22_14_07_09.png

I don't see why the VFB is not sending data out? My VDMA buffer is set to 1024 lines which should allow a lot more data to leave than just the first 2 lines:

gregbalke_0-1624396359045.png

gregbalke_0-1624397250907.png

The DMA buffers are also much larger than 1 frame in size so there's no way they are filling up after 2 lines. I also double checked the addresses and they are correct.

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nathanx
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Registered: ‎08-01-2007

You can dump all MIPI CSI-2 RX SS IP registers, to make sure if it works fine, something should be observed if MIPI IP does not work good.

gregbalke
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Registered: ‎04-08-2021

I traced through the entire signal path and discovered the signal just disappeared on the stretch between the video_out and S_AXIS_S2MM of the axi_vdma (the red connection). I ended up directly connecting the outputs/inputs and everything started working... Please report this to the developers as this consumed a huge amount of time and is damaging to my trust of the block diagram system.

gregbalke_0-1624474621451.png

To note: When I probed the synthesized output of the VFB (Video Format Bridge), it showed signals coming out so I believe the protocol is correct as RAW12. I noticed this issue is similar to @saiwing_hit's https://forums.xilinx.com/t5/Video-and-Audio/MIPI-CSI-2-RX-Subsystem-RGB565-format-settings/td-p/1254713 but ended with a different result.

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