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Contributor
Contributor
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Registered: ‎11-10-2017

MIPI CSI2 Rx Subsystem can't complete Reset when I replace Video Frame Buffer Write IP with VDMA

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I am now trying to replace Video Frame Buffer Write IP with VDMA in this design.

In this design, the PCam camera which is connected via MIPI is recognized as V4L2 device (/dev/video0), and we can get image from camera on Linux on ZYBO.

This design uses PetaLinux tool to build Linux kernel.
https://github.com/Digilent/Zybo-Z7-20-base-linux

 

As is also said in [this topic], Video Frame Buffer Write only supports normal video format.
I want to process each pixel of image by HLS Core, decrease the data width, and  reduce the amount of data to transfer from camera to processor, so I need to use VDMA instead of Video Frame Buffer Write IP core.
For now, I don't insert HLS core, just put VDMA after removing Video Frame Buffer Write.

I connected VDMA's interrupt pin and control pin to the same place where frame buffer IP was originally connected.

 

Screenshot from 2018-10-12 17-50-41.png

 

I changed the description specifying DMA in the device tree (system_user.dtsi), and comment out the description about v_frmbuf_wr.

 

< dmas = <&axi_vdma_2 0>;
---
> dmas = <&v_frmbuf_wr_0 0>;

 

 

I build the PetaLinux project, but it caused Kernel Panic when linux is booting.
The error is the following.

> Xilinx CSI2 Rx Subsystem Soft Reset Timeout!

 

 

The source of this error message is device driver of MIPI CSI2RX SubSystem.

After the device driver resets the IP core, it waits for the IP core to enter the ready state, but it has timed out.
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/media/platform/xilinx/xilinx-csi2rxss.c

I refered the document of MIPI CSI2RX SubSystem, But I could not understand the reason why IP core can't complete reset.

 

 

I attached three files.

1) pl.dtsi -- the device tree which is generated automatically by PetaLinux on the basis of hdf file.

2) old_ol.dtsi -- pl.dtsi file before changing circuit in Vivado. this contains the description about v_frmbuf_wr.

3) system_user.dtsi -- the device tree which is manually written.

 

What is the reason? any suggestion?

Thanks in advance.

 

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Contributor
Contributor
1,342 Views
Registered: ‎11-10-2017

@karnanl

Thank you for your reply.

I'm sorry, I already solve the problem.

 

MIPI CSI2 RX Subsystem IP core has  the "video_aresetn" pin in addition to software reset via "csirxss_s_axi" pin.

In the original vivado design, the "video_aresetn" pin of mipi_csi2_rx_subsystem core is connected to GPIO of processor.

 

The original petalinux project doesn't refer to the newest version of linux kernel.

The old version of device driver resets the gpio pin which is specified in the device driver.

https://github.com/Digilent/linux-digilent/blob/1496c680c6df2e3911feed13aa9663a851bf30e9/drivers/media/platform/xilinx/xilinx-csi2rxss.c

But,the newest version doesn't.

https://github.com/Digilent/linux-digilent/blob/master/drivers/media/platform/xilinx/xilinx-csi2rxss.c

 

I used the newest linux driver. so, the "video_aresetn" pin is not resetted correctly.

This is the reson why MIPI CSI2 Rx Subsystem can't complete reset.

View solution in original post

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Xilinx Employee
Xilinx Employee
1,349 Views
Registered: ‎03-30-2016

Hello @nittax

 

If your design modification

- does not affect clock and reset of MIPI CSI-2 RX SS

- and you did not change the register setting of MIPI CSI-2 RX SS, then it should works.

 

I am not sure why the driver set the Timeout of "soft-reset in progress" = 1ms.

But could you please do some experiment with Timeout setting value ? ( with a bigger value )

 

-- PG232 does not guarantee that soft-reset will be completed within 1ms.

 

Thanks & regards

Leo

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Contributor
Contributor
1,343 Views
Registered: ‎11-10-2017

@karnanl

Thank you for your reply.

I'm sorry, I already solve the problem.

 

MIPI CSI2 RX Subsystem IP core has  the "video_aresetn" pin in addition to software reset via "csirxss_s_axi" pin.

In the original vivado design, the "video_aresetn" pin of mipi_csi2_rx_subsystem core is connected to GPIO of processor.

 

The original petalinux project doesn't refer to the newest version of linux kernel.

The old version of device driver resets the gpio pin which is specified in the device driver.

https://github.com/Digilent/linux-digilent/blob/1496c680c6df2e3911feed13aa9663a851bf30e9/drivers/media/platform/xilinx/xilinx-csi2rxss.c

But,the newest version doesn't.

https://github.com/Digilent/linux-digilent/blob/master/drivers/media/platform/xilinx/xilinx-csi2rxss.c

 

I used the newest linux driver. so, the "video_aresetn" pin is not resetted correctly.

This is the reson why MIPI CSI2 Rx Subsystem can't complete reset.

View solution in original post

Highlighted
Xilinx Employee
Xilinx Employee
1,324 Views
Registered: ‎03-30-2016

Thank you for sharing your experience @nittax

 

Regards

Leo

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