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AB24
Visitor
Visitor
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Registered: ‎02-10-2021

MIPI CSI2

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Hi,

While implementing csi2 with FPGA, The path follow cmos image sensor -->csi2 -->FPGA.

Is there  any way to increase physical distance between cmos image sensor  and FPGA  while following csi2 interface or it ll fixed to 30mm?

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bpatil
Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @AB24 

Xilinx MIPI CSI-2 RX IP v4.1 follows MIPI Specifications (MIPI CSI-2 standard v2.0 with underlying MIPI D-PHY standard v1.2). MIPI Alliance’s DPHY specifications are for relatively small devices such as smartphones and tablets. So, MIPI CSI-2 camera sensor reach is limited by MIPI specifications. 

Please check MIPI A-PHY specification for your requirement: https://www.mipi.org/mipi-white-paper-driving-wires-automotive 

You can also check for MIPI CSI-2 extension chipset available in market: For example: https://www.digikey.com/en/product-highlight/c/cel/thine-v-by-one-hs-transmitter-receiver-family 

Regards,
Bhushan

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bpatil
Xilinx Employee
Xilinx Employee
404 Views
Registered: ‎03-07-2018

Hi @AB24 

Xilinx MIPI CSI-2 RX IP v4.1 follows MIPI Specifications (MIPI CSI-2 standard v2.0 with underlying MIPI D-PHY standard v1.2). MIPI Alliance’s DPHY specifications are for relatively small devices such as smartphones and tablets. So, MIPI CSI-2 camera sensor reach is limited by MIPI specifications. 

Please check MIPI A-PHY specification for your requirement: https://www.mipi.org/mipi-white-paper-driving-wires-automotive 

You can also check for MIPI CSI-2 extension chipset available in market: For example: https://www.digikey.com/en/product-highlight/c/cel/thine-v-by-one-hs-transmitter-receiver-family 

Regards,
Bhushan

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Give Kudos to a post which you think is helpful and reply oriented.
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karnanl
Xilinx Employee
Xilinx Employee
382 Views
Registered: ‎03-30-2016

Hello @AB24 
# Pardon me, but I am not really understand with your question above.
   So, just adding my comments below.


Assuming that you are using UltraScale+ devices:
I believe MIPI D-PHY clock/data lanes interconnect is not limited to 30mm PCB trace. It should be able tobe implemented in various interconnect topology.
These interconnect may consist of several cascaded transmission line segments, such as, printed circuit boards, flex-foils, and cable connections. As long as the physical connection are implemented as a balanced differential, point-to-point transmission lines referenced to ground.


The most important things to adhere are the following requirement.
- HS signal level at FPGA pins are within AC/DC spec range mentioned by the spec Chapter9
- LP signal level at FPGA pins are within AC/DC spec range mentioned by the spec Chapter9
- HS data to clock Setup/Hold timing requirement.

Please notice that
-MIPI D-PHY spesification Chapter8 also define interconnect characteristic (insertion loss etc).
-Xilix UG583 chapter5 provides a basic guideline for user who wants to create a custom board.

 

Assuming that you are using 7-series devices:

As you already aware that 7-series device IO does not support MIPI D-PHY signal natively.
So many of AC/DC electrical requirement mentioned in MIPI D-PHY spec are not applicable in this case.

If this is the case, you need to do board simulation to ensure if your sensor output can be translated correctly into signal level that receivable of 7-series device IO spec.
XAPP894 provides a basic information how to implement resistor network to translate MIPI D-PHY signal to LVDS.
If you need use a longer interface for your system, you need to verify and simulate yourself to check if this is working.


Thanks
Leo


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mizan123
Participant
Participant
288 Views
Registered: ‎10-30-2018

Yes, it is possible to increase the physical distance between csi-2 interface and fpga using external cable. You need serializer and deserialzer for that. We are already using a similar setup.