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514 Views
Registered: ‎05-27-2018

MIPI CSI2RX with Aptina (Onsemi) AR0330

Hi,

We are using Xilinx MIPI CSI2RX subsystem 5.0 with Aptina AR0330 as DPHY TX on Zynq US+ MPSOC.

Sensor configuration

- MIPI 4-lane

- Line-rate 588Mbps

We are not able to receive MIPI data properly in our design. Below are the issues we are seeing.

1) Sensor's continuous tx clock mode enabled

Issue: Clock lane's "hs_rx_disable" not going low at all. Even though we confirmed that the clock is running, still "cl_stopstate" is stuck at "1". Below is the snapshot of chipscope signals.

continuos_enable.png

 

2) Sensor's continuous tx clock mode disabled

Issue: In this mode, we are seeing "hs_rx_disable" is going low. But Data received "rx_dl*_hs_dp_w" is kind of random. So, "sot error" and "sot sync error" interrupts are received. Below is the snapshot of the chipscope signals.

continuous_disable.png

 

From the datasheet, I can see that the MIPI subsystem is tested with AR0330. Can you suggest the recommended configuration of the sensor and MIPI subsystem?

 

Thanks in advance.

 

-Divyesh

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

Please kindly confirm.

1. Are you using VCCO=1.2V with MIPI_DPHY_DCI IO standard ?

   MIPI_DPHY_12.png
2. Is 240ohm external resistor correctly connected to VRP pin ?
     240ohm.png

Regards
Leo

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Registered: ‎05-27-2018

Hi Leo,

 

1) Yes,

2) Yes.

 

I would like to know the configuration Xilinx does while communicating with AR0330. It is mentioned in UG that Xilinx CSI2RX SS is compatible with AR0330.

The sensor only operates reliably in "continuous clock mode"(Confirmed by the sensor datasheet), But somehow Xilinx IP is not happy in "continuous clock mode". Because it is not de-asserting "hs_rx_disable" for clock lane in "continuous clock mode". But the HS clock is received, confirmed by Scope.

-Divyesh

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

I do not expect any issue if you are using MIPI_DPHY_DCI with 1.2V VCCO and 240ohm external resistor is correctly connected to VRP pin. Could you please share your MIPI CSI-2 RX XCI file and register dump ?

As mentioned in PG232 only 490Mbps@4lanes RAW10 usecase is tested with this sensor.
So, perhaps you could double check if sensor register is set correctly.
OnSemi_AR0330_MIPI.png

Did you follow MIPI CSI-2 RX reset as mentioned in Figure 3-8 ?
please ensure that MIPI CSI-2 RX is initialized while sensor is sending LP-11, not after sensor is running and sending video data  in HS mode.

reset_mipi_rx.png

Thanks
Leo

 

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Registered: ‎05-27-2018

Hi Leo,

I need to recheck if we can run the sensor in RAW10 mode. As we are using VFB, CSI2RX can not receive RAW10/RAW12 simultaneously. I will reconfigure CSI2RX and check the RAW10 mode.

Regarding the Reset Sequence,

I'm pretty sure that the sensor is sending LP11(enabled testmode in sensor) while CSI2RX in Reset. Then only CSI2RX will assert init_done and cl_stopstate and dl_stopstate. This is the behaviour of CSI2RX.

Can you tell me which mode(continuous clock mode or non-continuous clock mode) you have used in your RAW10 testing? I can observe that in non-continuous clock mode, sensor seems to be misbehaving.

-Divyesh

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

I cannot find your XCI file and register dump in your previous post.

>Can you tell me which mode(continuous clock mode or non-continuous clock mode) you have used in your RAW10 testing?

I can check with our development team on this. Please wait for feedback.
# BTW, I don't have AR0330 datasheet on my side.
   Could you please tell me which register on AR0330 to configure HS clock. (as continuous clock mode or non-continuous clock mode)

>I can observe that in non-continuous clock mode, sensor seems to be misbehaving.

From your previous ILA capture, it seems that both continuous clock and non-continous clock are not working.
Which one is correct ? Please kindly confirm.

BTW, We also tested AR0330 with 588Mbps@4 lanes and RAW12, using 7-series device.
So, as long as you can set AR0330 register correctly, I believe MIPI CSI-2 RX should have no issue.

TEST_7SERIES.png
Thanks
Leo

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Registered: ‎05-27-2018

Hi Leo,

Thanks for the reply.

Here is the required .xci. We have configured 800Mbps as bitrate. But we are seeing pll_lock and vtc_ready coming high at 588Mbps.

Below is the snippet of the datasheet. They marked this bit as reserved bit but the reset value suggests that it is set. So, combining with ila snapshot, I came to know that sensor might not support it. Maybe someone from your development team can also comment on this. 

Capture.JPG

 

 

 

 

 

FYI both modes are not working in our systems. But the behaviour of sensor/CSI2RX is different in both the modes. We can go for any mode provided it works reliably.

 

Thanks again,

Divyesh

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

>We have configured 800Mbps as bitrate. But we are seeing pll_lock and vtc_ready coming high at 588Mbps.

You need to configure MIPI CSI-2 RX with the exact sensor/tx line-rate you configured.
In this case 588Mbps (or 490Mbps), using MIPI CSI-2 RX/MIPI D-PHY RX for multiple line-rate usecase is not supported.

>They marked this bit as reserved bit but the reset value suggests that it is set. So, combining with ila snapshot, I came to know that sensor might not support it.

Looking at our source code , it seems we only using Continuous clock mode.
    {0x31BC, 0x8005}, // MIPI_TIMING_4

From AR0330 you shared above, it clearly marked as reserved, so I believe only continuous clock is supported.
On_Semi_cont.png

>Maybe someone from your development team can also comment on this

Perhaps, this is something you need to confirm with OnSemi.

BTW, could you please re-check if clock/data lanes P/N are not swapped in your system ?

Thanks
Leo

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Registered: ‎05-27-2018

Hi Leo,

Thanks for the reply. I will update the line-rate to 588Mbps and try it. If possible, can you share part of the source code for sensor configuration?

-Divyesh

Xilinx Employee
Xilinx Employee
338 Views
Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

>can you share part of the source code for sensor configuration?


Please let me confirm this request with our internal team.

Thanks & regards
Leo

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Registered: ‎05-27-2018

Hi Leo,

We are able to get proper MIPI data by doing minor changes in the Sensor configuration sequence.

-Divyesh

Xilinx Employee
Xilinx Employee
270 Views
Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

That is good to hear. Congratulation.

BTW, we cannot share our internal source code to set sensor register.
Please get a guidance from OnSemi to do AR0330 sensor configuration correctly.

Kind regards
Leo

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