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divyesh.sinojiya
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Registered: ‎05-27-2018

MIPI CSI2RX with LVDS IOSTANDARD in Zync US+ MPSOC

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Hi,

We are using Xilinx MIPI CSI-2 RX Subsystem v5.0. We are using it with LVDS i/os with VCCO=1.8V.

We can't use native DPHY i/o because we have other signals in the same bank with i/o standard LVCMOS18. 

We are seeing some strange issues in our case that "rxbyteclkhs" is toggling at high-speed(confirmed by running counter on this clock) line rate, "**_stopstate" signal is not going low. Below are our observation from chipscope signals.

1) init_done from Dphy is "1"

2) cl_stopstate and dlx_stopstate are always "1"

3) rst_seq_done is "1"

4) vtc_ready  is "1"

5) pll_lock is "1"

Can someone please help with this that why CSI2RX not able to receive high speed data?

-Divyesh

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divyesh.sinojiya
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Observer
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Registered: ‎05-27-2018

Hi Leo,

Changing the i/os to "MIPI_DPHY_DCI", I'm seeing stop state de-asserted by D'Phy.

Many thanks.

-Divyesh

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @divyesh.sinojiya 

stopstate signal is asserted, after MIPI D-PHY RX can observed LP-11 transmitted by sensors.
LP11_triggered_STOPSTATE.png

BTW, We can only recommend using MIPI CSI-2 RX and MIPI D-PHY RX with MIPI_DPHY_DCI IO (which need VCCO=1.2V).
This usecase is never tested internally.

Regards
Leo

divyesh.sinojiya
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Registered: ‎05-27-2018

Hello Leo,

Thanks for the reply.

In my case, stopstste is asserted on all clock and data lanes. But it is not de-asserted even though the sensor moved to HS signaling. 

What can be the challenges in using LVDS instead of MIPI_DPHY_DCI? We have hardware ready, so I can't change the VCCO.

Thanks in advance.

-Divyesh

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divyesh.sinojiya
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Registered: ‎05-27-2018

Hi Leo,

Changing the i/os to "MIPI_DPHY_DCI", I'm seeing stop state de-asserted by D'Phy.

Many thanks.

-Divyesh

View solution in original post

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