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2U3
Explorer
Explorer
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Registered: ‎05-25-2020

MIPI D-PHY IP does not work

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Hello,

I'm implementing a MIPI D-PHY IP.

A simulation for MIPI D-PHY has completed successfully. Especially, dl0_rxdatahs shows NO constant signal.

But when run on a board, the rxdatahs[0] seems to be low constant, while there seems to be MIPI data signals at both ends of terminal resistance R150.

Could anyone please tell me how to debug?

My top *.sv and *.xdc are shown below, and my chip is xc7z010clg400.

Thank you.


-----------------------------
my_top_test_dphy.sv
-----------------------------
`timescale 1ns / 1ps

module my_top_test_dphy (
input logic CLK125, RST_AL,
input logic rx_mipi_phy_if_0_clk_hs_n,
input logic rx_mipi_phy_if_0_clk_hs_p,
input logic rx_mipi_phy_if_0_clk_lp_n,
input logic rx_mipi_phy_if_0_clk_lp_p,
input logic [0:0]rx_mipi_phy_if_0_data_hs_n,
input logic [0:0]rx_mipi_phy_if_0_data_hs_p,
input logic [0:0]rx_mipi_phy_if_0_data_lp_n,
input logic [0:0]rx_mipi_phy_if_0_data_lp_p,
output logic PIN_F19, PIN_G19, PIN_H18, PIN_J19
);

// logic clk_in_125MHz;
logic core_rst_0;
logic init_done_0;
// logic rx_mipi_phy_if_0_clk_hs_n;
// logic rx_mipi_phy_if_0_clk_hs_p;
// logic rx_mipi_phy_if_0_clk_lp_n;
// logic rx_mipi_phy_if_0_clk_lp_p;
// logic [0:0]rx_mipi_phy_if_0_data_hs_n;
// logic [0:0]rx_mipi_phy_if_0_data_hs_p;
// logic [0:0]rx_mipi_phy_if_0_data_lp_n;
// logic [0:0]rx_mipi_phy_if_0_data_lp_p;
logic rx_mipi_ppi_if_0_cl_enable;
logic rx_mipi_ppi_if_0_cl_rxclkactivehs;
logic rx_mipi_ppi_if_0_cl_rxulpsclknot;
logic rx_mipi_ppi_if_0_cl_stopstate;
logic rx_mipi_ppi_if_0_cl_ulpsactivenot;
logic rx_mipi_ppi_if_0_dl0_enable;
logic rx_mipi_ppi_if_0_dl0_errcontrol;
logic rx_mipi_ppi_if_0_dl0_erresc;
logic rx_mipi_ppi_if_0_dl0_errsoths;
logic rx_mipi_ppi_if_0_dl0_errsotsynchs;
logic rx_mipi_ppi_if_0_dl0_errsyncesc;
logic rx_mipi_ppi_if_0_dl0_forcerxmode;
logic rx_mipi_ppi_if_0_dl0_rxactivehs;
logic rx_mipi_ppi_if_0_dl0_rxclkesc;
logic [7:0]rx_mipi_ppi_if_0_dl0_rxdataesc;
logic [7:0]rx_mipi_ppi_if_0_dl0_rxdatahs;
logic rx_mipi_ppi_if_0_dl0_rxlpdtesc;
logic rx_mipi_ppi_if_0_dl0_rxsynchs;
logic [3:0]rx_mipi_ppi_if_0_dl0_rxtriggeresc;
logic rx_mipi_ppi_if_0_dl0_rxulpsesc;
logic rx_mipi_ppi_if_0_dl0_rxvalidesc;
logic rx_mipi_ppi_if_0_dl0_rxvalidhs;
logic rx_mipi_ppi_if_0_dl0_stopstate;
logic rx_mipi_ppi_if_0_dl0_ulpsactivenot;
logic rxbyteclkhs_0;
logic system_rst_out_0;

logic [31:0] c;

initial begin
  rx_mipi_ppi_if_0_dl0_enable <= 1;
  rx_mipi_ppi_if_0_cl_enable <= 1;
  rx_mipi_ppi_if_0_dl0_forcerxmode <= 0;
  core_rst_0 <= 1;
  c <= 0;
end

always @ (posedge CLK125) begin
    if(RST_AL) begin
        if(c == 10000) begin
            core_rst_0 <= 0;
        end else begin
            c <= c + 1;
        end
    end else begin
        core_rst_0 <= 1;
        c <= 0;
    end
end

assign PIN_F19 = rx_mipi_ppi_if_0_dl0_rxdatahs[0];
assign PIN_G19 = rx_mipi_ppi_if_0_dl0_rxdatahs[1];
assign PIN_H18 = rx_mipi_ppi_if_0_dl0_rxdatahs[2];
assign PIN_J19 = core_rst_0;

design_1_wrapper # () design_1_wrapper_i (
.clk_in_125MHz ( CLK125 ),
.core_rst_0 ( core_rst_0 ),
.init_done_0 ( init_done_0 ),
.rx_mipi_phy_if_0_clk_hs_n ( rx_mipi_phy_if_0_clk_hs_n ),
.rx_mipi_phy_if_0_clk_hs_p ( rx_mipi_phy_if_0_clk_hs_p ),
.rx_mipi_phy_if_0_clk_lp_n ( rx_mipi_phy_if_0_clk_lp_n ),
.rx_mipi_phy_if_0_clk_lp_p ( rx_mipi_phy_if_0_clk_lp_p ),
.rx_mipi_phy_if_0_data_hs_n ( rx_mipi_phy_if_0_data_hs_n ),
.rx_mipi_phy_if_0_data_hs_p ( rx_mipi_phy_if_0_data_hs_p ),
.rx_mipi_phy_if_0_data_lp_n ( rx_mipi_phy_if_0_data_lp_n ),
.rx_mipi_phy_if_0_data_lp_p ( rx_mipi_phy_if_0_data_lp_p ),
.rx_mipi_ppi_if_0_cl_enable ( rx_mipi_ppi_if_0_cl_enable ),
.rx_mipi_ppi_if_0_cl_rxclkactivehs ( rx_mipi_ppi_if_0_cl_rxclkactivehs ),
.rx_mipi_ppi_if_0_cl_rxulpsclknot ( rx_mipi_ppi_if_0_cl_rxulpsclknot ),
.rx_mipi_ppi_if_0_cl_stopstate ( rx_mipi_ppi_if_0_cl_stopstate ),
.rx_mipi_ppi_if_0_cl_ulpsactivenot ( rx_mipi_ppi_if_0_cl_ulpsactivenot ),
.rx_mipi_ppi_if_0_dl0_enable ( rx_mipi_ppi_if_0_dl0_enable ),
.rx_mipi_ppi_if_0_dl0_errcontrol ( rx_mipi_ppi_if_0_dl0_errcontrol ),
.rx_mipi_ppi_if_0_dl0_erresc ( rx_mipi_ppi_if_0_dl0_erresc ),
.rx_mipi_ppi_if_0_dl0_errsoths ( rx_mipi_ppi_if_0_dl0_errsoths ),
.rx_mipi_ppi_if_0_dl0_errsotsynchs ( rx_mipi_ppi_if_0_dl0_errsotsynchs ),
.rx_mipi_ppi_if_0_dl0_errsyncesc ( rx_mipi_ppi_if_0_dl0_errsyncesc ),
.rx_mipi_ppi_if_0_dl0_forcerxmode ( rx_mipi_ppi_if_0_dl0_forcerxmode ),
.rx_mipi_ppi_if_0_dl0_rxactivehs ( rx_mipi_ppi_if_0_dl0_rxactivehs ),
.rx_mipi_ppi_if_0_dl0_rxclkesc ( rx_mipi_ppi_if_0_dl0_rxclkesc ),
.rx_mipi_ppi_if_0_dl0_rxdataesc ( rx_mipi_ppi_if_0_dl0_rxdataesc ),
.rx_mipi_ppi_if_0_dl0_rxdatahs ( rx_mipi_ppi_if_0_dl0_rxdatahs ),
.rx_mipi_ppi_if_0_dl0_rxlpdtesc ( rx_mipi_ppi_if_0_dl0_rxlpdtesc ),
.rx_mipi_ppi_if_0_dl0_rxsynchs ( rx_mipi_ppi_if_0_dl0_rxsynchs ),
.rx_mipi_ppi_if_0_dl0_rxtriggeresc ( rx_mipi_ppi_if_0_dl0_rxtriggeresc ),
.rx_mipi_ppi_if_0_dl0_rxulpsesc ( rx_mipi_ppi_if_0_dl0_rxulpsesc ),
.rx_mipi_ppi_if_0_dl0_rxvalidesc ( rx_mipi_ppi_if_0_dl0_rxvalidesc ),
.rx_mipi_ppi_if_0_dl0_rxvalidhs ( rx_mipi_ppi_if_0_dl0_rxvalidhs ),
.rx_mipi_ppi_if_0_dl0_stopstate ( rx_mipi_ppi_if_0_dl0_stopstate ),
.rx_mipi_ppi_if_0_dl0_ulpsactivenot ( rx_mipi_ppi_if_0_dl0_ulpsactivenot ),
.rxbyteclkhs_0 ( rxbyteclkhs_0 ),
.system_rst_out_0 ( system_rst_out_0 )
);

endmodule

-----------------------------
test_dphy.xdc
-----------------------------
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports CLK125]
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports RST_AL]
set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 DRIVE 12 } [get_ports PIN_F19]
set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 DRIVE 12 } [get_ports PIN_G19]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 DRIVE 12 } [get_ports PIN_H18]
set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 DRIVE 12 } [get_ports PIN_J19]

set_property INTERNAL_VREF 0.6 [get_iobanks 34]
set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVDS_25 } [get_ports { rx_mipi_phy_if_0_clk_hs_n }];
set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVDS_25 } [get_ports { rx_mipi_phy_if_0_clk_hs_p }];
set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVDS_25 } [get_ports { rx_mipi_phy_if_0_data_hs_n[0] }];
set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVDS_25 } [get_ports { rx_mipi_phy_if_0_data_hs_p[0] }];
set_property -dict { PACKAGE_PIN W20 IOSTANDARD HSUL_12 } [get_ports { rx_mipi_phy_if_0_clk_lp_n }];
set_property -dict { PACKAGE_PIN V20 IOSTANDARD HSUL_12 } [get_ports { rx_mipi_phy_if_0_clk_lp_p }];
set_property -dict { PACKAGE_PIN U20 IOSTANDARD HSUL_12 } [get_ports { rx_mipi_phy_if_0_data_lp_n[0] }];
set_property -dict { PACKAGE_PIN T20 IOSTANDARD HSUL_12 } [get_ports { rx_mipi_phy_if_0_data_lp_p[0] }];

sim_dphy.png
exp_dphy.png
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1 Solution

Accepted Solutions
watari
Teacher
Teacher
386 Views
Registered: ‎06-16-2013

Hi @2U3 

 

>4. Could you tell me where can I get MIPI D-PHY IP register value? Instead, I upload IP config dialog.

 

Would you make sure an address of MIPI D-PHY IP as below by Vivado ?

 

1. Open block design

2. Click Address Editor tab

3. You can find an address on MIPI D PHY

 

Also, this @karnanl 's comment is helpful for debugging.

Would you refer it, too ?

 

https://forums.xilinx.com/t5/Video-and-Audio/MIPI-RX-issue-using-Spartan-7/m-p/1210971/highlight/true#M36982

 

Best regards,

View solution in original post

11 Replies
watari
Teacher
Teacher
493 Views
Registered: ‎06-16-2013

Hi @2U3 

 

Did you make sure voltage level on each points ?

Also, what is your target frequency rate ?

And are you using proper reference clock to ISERDES ?

 

Best regards,

karnanl
Xilinx Employee
Xilinx Employee
459 Views
Registered: ‎03-30-2016

Hello @2U3 

1. MIPI D-PHY RX needs a free-run 200MHz clock.
    Could you please ensure you have a free-run 200MHz clock running in your FPGA design ?

2. It seems you are using resistor network mentioned in XAPP894.
    Are those resistors and XC7Z010CLG400 are on the same board ?
    # Please see also SP701 board schematic. ( LINK  )
        We suggest to place all these resistors near FPGA.
       SP701_res_netwrk2.png

3. I cannot get much detailed information from your scope capture below.
    You should move (A,B) as close as possible to FPGA pins, and please share more detailed oscilloscope waveform. ( So, we can double check the input level in your board )

    # Looking at figure below, it seems that LP-->HS transition signal may not correctly recognized by MIPI D-PHY RX IP, so D-PHY IP is still in LP mode.
   LP_signals_are_not_good.png

4. Could you please share the following MIPI D-PHY IP register value ?
          0x0 : CONTROL Register
          0x4 : IDELAY_TAP_VALUE
          0x18 : CL_STATUS for clock Lane.
          0x1C~0x28 : DL0_STATUS for data lanes 1 to 4.
# I am suspecting clock/data lane are still in LP mode.

Kind regards
Leo


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2U3
Explorer
Explorer
427 Views
Registered: ‎05-25-2020

I measured voltages at both ends of R150 as shown in a figure, which is connected to P-N output pair from a camera. Here, FPGA is not connected.

MIPI data signal seems to be correct, but MIPI clock signals keep below 600mV. It may be caused by not enough band width of my oscilloscope. And, I think there could not be observed LP part in the MIPI clock signals. Frequency of the MIPI clock signals are about 116MHz. (Last week, these are 133MHz ???)

Can these are detected at HSUL_12 pins?

And, do you know where can one see typical MIPI data and clock signals?

 

I'm sorry that I do not know what the ISERDES is, and in this experiment, ISERDES may not be concerned.

 

Thank you.

 

mipi_signal_point.png
mipi_signal.png
2U3
Explorer
Explorer
425 Views
Registered: ‎05-25-2020

1. Yes, I supply 200MHz to the IP using Clocking Wizard IP as shown in a figure.

2. No, these are not on a board as shown in a figure. And NO chip resistances are used. As voltage supplied to the bank is 3.3V, I can not use internal termination.

When a frequency of MIPI clock is low as 116MHz, I think these could work well in spite of such bad SI. Is it correct?

3. I've uploaded more detailed oscilloscope waveform. MIPI data LP voltages are 630mV. (cf. it is 1.3V for Raspberry Pi camera)

4. Could you tell me where can I get MIPI D-PHY IP register value? Instead, I upload IP config dialog.

Thank you.

 

dphy_design.png
dphy_design_200.png
mipi_signal_point2.png
dphy_config.gif
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watari
Teacher
Teacher
387 Views
Registered: ‎06-16-2013

Hi @2U3 

 

>4. Could you tell me where can I get MIPI D-PHY IP register value? Instead, I upload IP config dialog.

 

Would you make sure an address of MIPI D-PHY IP as below by Vivado ?

 

1. Open block design

2. Click Address Editor tab

3. You can find an address on MIPI D PHY

 

Also, this @karnanl 's comment is helpful for debugging.

Would you refer it, too ?

 

https://forums.xilinx.com/t5/Video-and-Audio/MIPI-RX-issue-using-Spartan-7/m-p/1210971/highlight/true#M36982

 

Best regards,

View solution in original post

2U3
Explorer
Explorer
370 Views
Registered: ‎05-25-2020

Address Editor window seems not to be available for a slave.

Data flow of the IP is RX, so it is a slave? There is no "Address Editor" in a "Diagram" that I uploaded on 02-25-2021 04:58 AM.


Thank you.

 

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watari
Teacher
Teacher
360 Views
Registered: ‎06-16-2013

Hi @2U3 

 

Would you change parameter as enable on "Control and Debug" to investigate the route cause ?

 

Best regards,

2U3
Explorer
Explorer
328 Views
Registered: ‎05-25-2020

I activated a checkbox for "Enable AXI-4 Lite Register I/F," then some AXI ports appeared and I supplied another 100MHz clock to s_axi_aclk. Is it that you intended?

But, there is no data in the Address Editor pane as shown in a figure.

Could you please tell me what should I do as next?

BTW, I'm afraid of that MIPI data LP voltages would be too low, as these are 630mV while that of Raspberry Pi camera are 1.3V.

And, I think a MIPI camera can work whether RX is connected or not. Is it right? Some response from RX is needed? 


Thank you.

dphy_design2.png
dphy_addr_edit.png
2U3
Explorer
Explorer
312 Views
Registered: ‎05-25-2020

After referring a topic you provided, I've got some video signals from MIPI D-PHY IP as shown in a figure, these are bit0, bit1, bit2 and bit3 of rx_mipi_ppi_if_0_dl0_rxdatahs, under a setting of 20us and 5V.

The reason that MIPI D-PHY IP did not work is wrong sequence of resets.

One should first reset MIPI D-PHY IP and power on MIPI camera.

I do thank everyone who gives me advices.

Thank you.

dphy_signal4bit.png
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karnanl
Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎03-30-2016

Hello @2U3 
# Just adding my two cents here.

One suggestion is
If you want to test MIPI camera using XAPP894 resistor network, We would suggest to use SP701 board as a start point.
Xilinx has a MIPI CSI-2 RX Example design using SP701. (Please see PG232 for detailed information)
This example working at 900Mbps@2lane.

>MIPI data signal seems to be correct, but MIPI clock signals keep below 600mV. It may be caused by not enough band width of my oscilloscope. And, I think there could not be observed LP part in the MIPI clock signals. Frequency of the MIPI clock signals are about 116MHz. (Last week, these are 133MHz ???)
>Can these are detected at HSUL_12 pins?

These signal behave like MIPI D-PHY signal during LP-mode -> HS-mode transition,
but signal amplitude are below the spec. I don't think MIPI D-PHY IP can recognize this 600mV level as LP-11.

>And, do you know where can one see typical MIPI data and clock signals?

You can check MIPI D-PHY spec for detailed information.
MIPI_DPHY_DC_Spec.png


Kind regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

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2U3
Explorer
Explorer
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Registered: ‎05-25-2020

I see that these signals may not be image data signal. As next to do, I will check using a camera module of another model.

Thank you.

 

 

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