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leoleonis
Observer
Observer
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Registered: ‎07-15-2019

MIPI D-PHY RX asyncrounus

leoleonis_0-1613038461548.png

 

hello,

I use the MIPI - DPHY Core 4.3, with my own receiver . This receiver uses the rxsync outputs of the PPI Interface and the highspeed Data Lanes. 
usually the rxsync pulses are synchronous, but sometimes not, as you see in the screenshot. 
for the next frame, it will be synchronous again. 
looking on an oscilloscope, lanes are always synchronous. 

is there a reason for that? do I have to handle this in the receiver?

thank you, Leo Rögner

 

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016


Hello @leoleonis 

>is there a reason for that? do I have to handle this in the receiver?

Yes please, MIPI D-PHY RX IP does not perform any byte alignment between data lanes. Please expect 1 rxbyeclkhs clock skew between data lanes.
PG202 describes this behavior, CSI-2 layer (or other protocol IP) needs to align those data lanes.

MIPI_DPHY_does_not_perform_byte_alg.png

Kind regards
Leo


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leoleonis
Observer
Observer
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Registered: ‎07-15-2019

ok, thank you. what exactly is reported by dlx_errsotsynchs ? In former designs we had a transmitter with sometimes unaligned Lanes for 2 or 6 highspeed half-clock cycles. Some customer reported than a problem in their receiver, so we redesigned it for always aligned lanes. However, in test we want to find out, if Lanes are aligned. With this D'PHY core this will not be possible, will it?

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

>what exactly is reported by dlx_errsotsynchs ?

It is written in PG202. IF SoT leader sequence is corrupted, errsotsynchs will be asserted.


>In former designs we had a transmitter with sometimes unaligned Lanes for 2 or 6 highspeed half-clock cycles. Some customer reported than a problem in their receiver, so we redesigned it for always aligned lanes. However, in test we want to find out, if Lanes are aligned. With this D'PHY core this will not be possible, will it?


Yes, this is IP spec. If you are using MIPI D-PHY RX IP, please expect 1 rxbyeclkhs clock skew between data lanes.


Thanks
Leo


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leoleonis
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Registered: ‎07-15-2019

understood and done like this - however, there are still customers reporting, that their receiver (up to 1Git/sec, without deskew..) doesn't work with asynchronous lanes. therefore we designed the transmitter for synchronous lanes. Is there a solution to test this? it should be easy to get this Information out of the MIPI-DPHY-Core. I had done this on 7000er zynq, with a DPHY-Bridge solution. but on ultrascale+ we wanted to use automatic deskew, and used therefore the MIPI-DPHY Core from xilinx.

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

Even, if your MIPI D-PHY TX is sending data at exactly the same time.
You may see 1 rxbyeclkhs skew on Xilinx MIPI D-PHY RX data lane output. Higher layer protocol needs to compensates this data lanes skew.

If your MIPI D-PHY TX does not send data at same time ( you call it asynchronous),
You may see more than 1 rxbyeclkhs skew on Xilinx MIPI D-PHY RX data lane output.

>but on ultrascale+ we wanted to use automatic deskew, and used therefore the MIPI-DPHY Core from xilinx.

I believe MIPI D-PHY RX IP for UltraScale+ does not feature to compensate skew between data lanes.
( It should be same as IP for 7-series )

Regards
Leo


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leoleonis
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Registered: ‎07-15-2019

for 7-Series I did not use the DPHY core from xilinx, I built the SoT Synchronization behind a SERDES by myself. 
for 1Gibt /sec this was o.k., and it was possible for us to trigger on not aligned Lanes.

for 2Git/sec we moved to ultrascale+ and DPHY-Core from xilinx.

the question is, if there is a solution to test for not aligned lanes with the Xilinx-DPHY core? 

 

 

 

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @leoleonis 

>the question is, if there is a solution to test for not aligned lanes with the Xilinx-DPHY core?

Pardon me I am not so clear with this question.

Xilinx MIPI D-PHY RX core clock lanes are working independently. There is no such as a status register to judge whether data lanes output has a skew or not.
Users need to monitor PPI I/F (RXSYNCHS) of MIPI D-PHY RX to know this.

RXSYNCHS.png

Hope this helps.

Regards
Leo


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