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Visitor
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Registered: ‎02-17-2020

MIPI D-PHY TO HDMI and Vice-versa

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Hello guys,

I am trying to convert a MIPI D-PHY video signal to HDMI and vice versa. The problem I am running into is that I am currently using a mojo v3 dev board which is based on the Spartan 6. However, the Spartan 6 FPGA pins do not support D-PHY. I found (https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf) which explains how to build a D-PHY interface on the Spartan 6, but as I am flexible on the fpga to use, I was hoping to find more recent boards that do support D-PHY. I understand that UltraScale+, and 7 series FPGA's support the logiCORE IP which can be used to implement D-PHY (https://www.xilinx.com/support/documentation/ip_documentation/mipi_dphy/v4_2/pg202-mipi-dphy.pdf). What would be the best direction for me? Is it better to implement XAPP894 on the Spartan 6 or should I get a 7 series FPGA and use logiCORE? Also, does Xilinx offer any dev kits that support D-PHY and have HDMI ports so I can quickly build and test my solutions?

 

Regards.

 

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Moderator
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Registered: ‎11-09-2015

Hi @pascaldao 

There are 2 things to differentiate when talking about D-PHY: the IO termination and the IP.

Ultrascale+ devices have a MIPI D-PHY termination integrated in their devices. So no external devices are required.

On the other side 7-series devices do not have the MIPI D-PHY IO termination, so the only way to meet the D-PHY electrical requirements is by using an external PHY as mentioned in  (https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf). As you have found the same will apply for Spartan-6

Now there is the Xilinx D-PHY IP. So this IP only supports 7-Series and Ultrascale+. So if you want to start directly with it, you might want to select these devices.

There are multiple board which can support MIPI D-PHY (they use MIPI CSI-2 RX) and output to HDMI:

  • The Spartan-7 board, SP701, has the external phy solution mentioned in xapp894 and an HDMI output which is also using an external component, the ADV7511. This board will only be able to output 1080p60 max. There is already an example which is taking the output on a MIPI CSi2 camera and output on the HDMI output. Refer to PG232 Chapter 5
  • The ZCU102, ZCU104 and ZCU106, based on Ultrascale+ devices, which do not require the external PHY. With this boards, HDMI can support up to 8K. There is a bare-metal (no OS) example design on the ZCU102 (showing 4K) taking the output on a MIPI CSi2 camera and output on the HDMI output. Refer to PG232 Chapter 5 Also, there are 2 examples running on linux OS, the ZCU102 TRD and ZCU106 VCU TRD.

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Hi @pascaldao 

There are 2 things to differentiate when talking about D-PHY: the IO termination and the IP.

Ultrascale+ devices have a MIPI D-PHY termination integrated in their devices. So no external devices are required.

On the other side 7-series devices do not have the MIPI D-PHY IO termination, so the only way to meet the D-PHY electrical requirements is by using an external PHY as mentioned in  (https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf). As you have found the same will apply for Spartan-6

Now there is the Xilinx D-PHY IP. So this IP only supports 7-Series and Ultrascale+. So if you want to start directly with it, you might want to select these devices.

There are multiple board which can support MIPI D-PHY (they use MIPI CSI-2 RX) and output to HDMI:

  • The Spartan-7 board, SP701, has the external phy solution mentioned in xapp894 and an HDMI output which is also using an external component, the ADV7511. This board will only be able to output 1080p60 max. There is already an example which is taking the output on a MIPI CSi2 camera and output on the HDMI output. Refer to PG232 Chapter 5
  • The ZCU102, ZCU104 and ZCU106, based on Ultrascale+ devices, which do not require the external PHY. With this boards, HDMI can support up to 8K. There is a bare-metal (no OS) example design on the ZCU102 (showing 4K) taking the output on a MIPI CSi2 camera and output on the HDMI output. Refer to PG232 Chapter 5 Also, there are 2 examples running on linux OS, the ZCU102 TRD and ZCU106 VCU TRD.

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Visitor
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Registered: ‎02-17-2020

@florentw 

Thank you so much for such a detailed and comprehensive answer, I have all the information I need. Just to be clear though, the Spartan-6 is NOT 7-series correct? This is to clarify the 1st line in your third paragraph. I think there might be a typo.

Thanks a lot!

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Moderator
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Registered: ‎11-09-2015

Hi @pascaldao 

Correct Spartan-6 is not a 7-series. What I meant is that you need the external PHY for 7-series and as well for Spartan-6 (and probably all current generations except US+).

I tried to edit my previous reply to make it more clear.

Sorry, English is not my mother's tongue


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎02-17-2020

@florentw 

 

Got it, thank you so much!

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Registered: ‎02-17-2020

@florentw 

Sorry, I have one more follow up question. Would it be possible to generate a clock on the Spartan-7 in order to do better than 1080p@60Hz ?

 

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Moderator
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Registered: ‎11-09-2015

Hi @pascaldao 

It is not about the clock inside the FPGA. You could do multiple pixels per clock which could help as well.

The limitation is a limitation of the ADV7511. But also, if you want to do HDMI directly from the device, you would need to use gigabit transceivers (GT). Spartan-7 does not have any GT


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
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Registered: ‎02-17-2020

I see, thank you.

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@florentw 

Will systems developed on the SP701/XC7S100 easily port on other Spartan-7's, for example the XC7S50 or XC7S25. We might need smaller packaging for our application? Regards.

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Xilinx Employee
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Registered: ‎03-30-2016

Hello @pascaldao 
# Just adding my two cents.

I would suggest to use US+ device for MIPI IP implementation.
US+ device has a native support for MIPI D-PHY specification.

XAPP894 resistor network is not a compliant MIPI solution.
It is expected to work with a typical MIPI D-PHY signals. ( But for D-PHY signal with low Common-mode voltage or low swing level resistor network may not be a robust solution). If you are using 7-series FPGA, Meticom external PHY is recommended.

BTW, as you may already aware that Xilinx MIPI IPs does not support Spartan-6.


Regards
Leo

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Visitor
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Registered: ‎02-17-2020

@karnanl 

Thanks for contributing. I am looking at US+ dev kits. One more question. Are there any solutions that aim to enable bridging a video stream from USC-C to MIPI DSI?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @pascaldao 

>Are there any solutions that aim to enable bridging a video stream from USC-C to MIPI DSI?

Xilinx does not offer this IP solution.
I am not aware/sure if 3rd party vendor has it.

Regards
Leo

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Visitor
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Registered: ‎02-17-2020

Understood, using the the SP701 would it be possible to take in HDMI as input and output on dual MIPI-DSI? This would be using the HDMI port as input, not output and would require to access additional pins on the Spartan 7 for the second MIPI display, because of the SP701 only has one MIPI-DSI interface. If that is not possible, do you guys offer solutions that can support taking HDMI in and outputting on multiple MIPI-DSI displays ?

Thanks.

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