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Visitor
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Registered: ‎12-11-2018

MIPI D-PHY v1.2 TX implementation on the VU9P device on a VCU118 board

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We are designing an FMC+ daughter card for the VCU118 board to support multiple MIPI D-PHY v1.2 TX connectors. For implementing the MIPI D-PHY TX controller in the FPGA, we are referring to the following documents:

* PG202 (v4.1) December 10, 2018

* XAPP1339 (v1.0) October 31, 2018

From these documents it appears that the "LP Receiver" functionality (reverse data communication) is NOT supported by the MIPI D-PHY controller. Isn't this functionality required in a host device to be compliant to the MIPI specification v1.2 ? 

Thanks,

Ramana

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Ramana @ramanar

>From these documents it appears that the "LP Receiver" functionality (reverse data communication)
>is NOT supported by the MIPI D-PHY controller. Isn't this functionality required in a host device to be
>compliant to the MIPI specification v1.2 ? 


Xilinx MIPI D-PHY IP (at present 2018.3), only support MIPI D-PHY spesification ver1.1

XF_0214_IP_support_11.png

Bi-directional data lane is an optional features of MIPI D-PHY specification. ( both on ver1.1 and ver1.2)
Please refer to chapter 4 of the specification document.


XF_0214_DPHY_BIDIRECT_OPTIONAL.png

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
644 Views
Registered: ‎03-30-2016

Hello Ramana @ramanar

>From these documents it appears that the "LP Receiver" functionality (reverse data communication)
>is NOT supported by the MIPI D-PHY controller. Isn't this functionality required in a host device to be
>compliant to the MIPI specification v1.2 ? 


Xilinx MIPI D-PHY IP (at present 2018.3), only support MIPI D-PHY spesification ver1.1

XF_0214_IP_support_11.png

Bi-directional data lane is an optional features of MIPI D-PHY specification. ( both on ver1.1 and ver1.2)
Please refer to chapter 4 of the specification document.


XF_0214_DPHY_BIDIRECT_OPTIONAL.png

Thanks & regards
Leo

View solution in original post