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Contributor
Contributor
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Registered: ‎01-03-2019

MIPI DPHY 4.1: use cl/dl_enable to close ppi flow

If  i  use  cl/dl_enable(1'b0)  to turn off  ppi flow ,then i turn on  ppi flow(cl/dl_enable =1'b1).These is no rst  operation. DPHY  can work well?

Accroding to PG202 (v4.1)   ,"When Enable is Low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state", turn off  ppi flow immediately ,can make inter logic in Dphy  into an uncertain state? 

360截图20201020190257086.jpg
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Xilinx Employee
Xilinx Employee
135 Views
Registered: ‎03-30-2016

Hello @taylor91 

I do not expect any issue with cl/dl_enable toggling without reset.
But for sure, MIPI D-PHY RX will send a garbage HS packet if you disable clock/data lane.

Do you see any unexpected behavior ? 

Kind regards
Leo

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