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shahan.a
Participant
Participant
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Registered: ‎06-25-2019

MIPI_DPHY_DCI IOstandard

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What are the input signal voltage levels supported by MIPI_DPHY_DCI IOstandard? Does it support 0.33 V input signal? When trying to view the IOstandard of a pin in I/O Planning layout in Vivado after manually writing IOstandard of a pin as MIPI_DPHY_DCI to a constraints file. The IOstandard is seen to be in red colour(I have attached a screenshot). What would be the reason for this? I had mentioned Multiple IOstandards in a single bank(I understand this shouldn't be done). Is it because of this DRC violation the IOstandard is seen in red colour?

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MIPI interface.jpg
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karnanl
Xilinx Employee
Xilinx Employee
918 Views
Registered: ‎03-30-2016

Hello,

>MIPI_DPHY_DCI input would be required for future expansion of a project I am trying to implement. I don't have experience with this standard and to prevent any unforeseen issue in the future I wanted to understand more about this standard.

Xilinx supports MIPI_DPHY_DCI IO standard usage, using MIPI D-PHY IP. (Please see also PG202)
PG202 Appendix C , has a pin-assignment guidance for UltraScale+ devices.

Create a simple MIPI D-PHY design

>I would be glad if you could refer some documents regarding this interface and io standard.

The following docs should be a good place to start.
- DS925/DS923/DS922 : Datasheet for UltraScale+ devices
- PG202.
- UG571.

>Does it support i/o signal levels of 0.33V?

Pardon me, I do not understand this question. (It is not clear whether you are interested in differential or single-ended signal , or whether 0.33V is signal min/max level or common-mode voltage )

BTW, if you are intrested in MIPI D-PHY electrical spec, please go to mipi.org to get MIPI D-PHY specification.
https://members.mipi.org/wg/All-Members/document/folder/8354

Please see chapter9 for Electrical spec detailed information.
MIPI_DPHY_DCI IO standard is compliance with MIPI D-PHY spec, so it can receives both HS differential signal and LP single-ended signal.

Kind regards
Leo


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spec1.png
spec_hs.png
spec_lp.png
4 Replies
karnanl
Xilinx Employee
Xilinx Employee
956 Views
Registered: ‎03-30-2016

Hello @shahan.a 

We don't recommend using MIPI_DPHY_DCI as a standalone IO.
We only support using Xilinx MIPI IP.
      MIPI D-PHY RX - (PG202
      MIPI CSI-2 RX   - (PG232)

May I know why you want to use MIPI_DPHY_DCI as input pins (without using MIPI D-PHY RX IP) ?

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
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shahan.a
Participant
Participant
931 Views
Registered: ‎06-25-2019

MIPI_DPHY_DCI input would be required for future expansion of a project I am trying to implement. I don't have experience with this standard and to prevent any unforeseen issue in the future I wanted to understand more about this standard.

I would be glad if you could refer some documents regarding this interface and io standard.

Does it support i/o signal levels of 0.33V?

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
919 Views
Registered: ‎03-30-2016

Hello,

>MIPI_DPHY_DCI input would be required for future expansion of a project I am trying to implement. I don't have experience with this standard and to prevent any unforeseen issue in the future I wanted to understand more about this standard.

Xilinx supports MIPI_DPHY_DCI IO standard usage, using MIPI D-PHY IP. (Please see also PG202)
PG202 Appendix C , has a pin-assignment guidance for UltraScale+ devices.

Create a simple MIPI D-PHY design

>I would be glad if you could refer some documents regarding this interface and io standard.

The following docs should be a good place to start.
- DS925/DS923/DS922 : Datasheet for UltraScale+ devices
- PG202.
- UG571.

>Does it support i/o signal levels of 0.33V?

Pardon me, I do not understand this question. (It is not clear whether you are interested in differential or single-ended signal , or whether 0.33V is signal min/max level or common-mode voltage )

BTW, if you are intrested in MIPI D-PHY electrical spec, please go to mipi.org to get MIPI D-PHY specification.
https://members.mipi.org/wg/All-Members/document/folder/8354

Please see chapter9 for Electrical spec detailed information.
MIPI_DPHY_DCI IO standard is compliance with MIPI D-PHY spec, so it can receives both HS differential signal and LP single-ended signal.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

spec1.png
spec_hs.png
spec_lp.png
shahan.a
Participant
Participant
885 Views
Registered: ‎06-25-2019

@karnanl 

Thanks