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Visitor
Visitor
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Registered: ‎09-19-2019

MIPI DPHY

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I'm using the MIPI DPHY IP.I just wonder whether the DSI port can be used as receiver or not? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @mason_zhou 

Yes, we highly recommended to set MIPI D-PHY RX line-rate to match MIPI signal liner-rate sent by sensors.

Regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @mason_zhou 

>I'm using the MIPI DPHY IP.I just wonder whether the DSI port can be used as receiver or not?

I am not so clear with your question.

Xilinx has 4 MIPI IPs
PG202 : MIPI D-PHY v4.2
PG232 : MIPI CSI-2 Receiver Subsystem v4.1
PG260 : MIPI CSI-2 Transmitter Subsystem v2.1
PG238 : MIPI DSI Transmitter Subsystem v2.0

If you want to implement MIPI DSI RX in Xilinx FPGA. It is possible since MIPI D-PHY IP can support both RX and TX.
# Please note that we do not support bi-directional MIPI D-PHY I/F. (or Link turn-around)

But unfortunately Xilinx does not have DSI Receiver IP solution, so you might need to create the IP yourself or find it from 3rd party vendor.

Thanks & regards
Leo

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Visitor
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Registered: ‎09-19-2019
I'm sorry for my describtion!My design has both RX and TX implemented with MIPI D-DPHY. So I want to know if any pin of HP can be contrained as RX or just some 'special pin in HP bank' can be constrained as RX.
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @mason_zhou 

Yes, any UltraScale+ HP I/O pin can be used as MIPI D-PHY TX or RX pin.

BTW, if you are planning to use MIPI D-PHY IP for UltraScale+ device , please read PG202 Appendix C. (https://www.xilinx.com/support/documentation/ip_documentation/mipi_dphy/v4_2/pg202-mipi-dphy.pdf)
Hope this helps

Regards
Leo

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Visitor
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Registered: ‎09-19-2019

OK!Thanks so much.By the way,I want to ask another question.When I implement the D-DPHY as RX,I also have to configure the Line_rate.But I think the Line_rate should be decided by camera with TX dphy.So my question is whether the Line_rate of camera with TX dphy must be compatiable with the Line_rate of RX dphy which I implement.  

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Visitor
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Registered: ‎09-19-2019
OK!Thanks so much.By the way,I want to ask another question.When I implement the D-DPHY as RX,I also have to configure the Line_rate.But I think the Line_rate should be decided by camera with TX dphy.So my question is whether the Line_rate of camera with TX dphy must be compatiable with the Line_rate of RX dphy which I implement.
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Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎03-30-2016

Hello @mason_zhou 

Yes, we highly recommended to set MIPI D-PHY RX line-rate to match MIPI signal liner-rate sent by sensors.

Regards
Leo

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