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jhallen
Observer
Observer
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Registered: ‎03-23-2017

MIPI DSI Tx subsystem startup

Hello,

I'm trying to implement a reduced latency video pipeline, so I want the sycnronize the video source with the destination to keep buffering to a minimum.  The MIPI DSI Tx subsystem has its own video timing generator within it, so I need to be careful how I synchronize with it.  There is a core enable bit.  Can anyone tell me if the video timing generator in the DSI Tx is free running, or does it start when the core enable bit is asserted?  If it's free running, then there can be a one frame delay between core enable, and video starts going.  If the timing generator starts when core enable is asserted, then there is a few lines delay only.

Some related questions: Is there any easier way to start the DSI Tx from FPGA logic other than generating AXI transactions?  I was hoping for a control line...

Is there any way to access the vsync and hsync generated by the DSI Tx core?

Thanks!

Joe

 

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karnanl
Xilinx Employee
Xilinx Employee
780 Views
Registered: ‎03-30-2016

Hello Joe @jhallen 

1. The timing generator inside MIPI DSI controller will start when the core enable bit is asserted.

2. Unfortunately, user cannot access vsync/hsync directly.
As mentioned in the PG238 that The controller must be programmed with required timing values for video data transfer. Please refer Example Timing Register Calculations in PG238 Chapter3.

Regards
Leo

karnanl
Xilinx Employee
Xilinx Employee
598 Views
Registered: ‎03-30-2016

Hello Joe @jhallen 

Do you have any update on this post ?
If your question is answered or issue solved, would you be able to share your solution ? so other forum users can learn from your experience.

Thanks & regards
Leo

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jhallen
Observer
Observer
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Registered: ‎03-23-2017

Oh, I did get this to work, I mean I could start a DSI Tx subsystem by having an FPGA state machine generate an AXI transaction to set the enable bit.  However, I then ran into the issue where the sync timing within the DSI core is not calculated correctly, see this thread:

 https://forums.xilinx.com/t5/Video/MIPI-DSI-Transmitter-Subsystem-sync-timing/td-p/1034591 

This second issue ultimately prevented me from using the Xilinx DSI IP.  I ended up writing my own IP (I now have DSI Tx, DSI Rx and CSI Rx and I will soon also have CSI Tx).

 

Thanks!

Joe

 

 

yuko.2828
Adventurer
Adventurer
545 Views
Registered: ‎12-27-2018

Joe, Wow ! You have created your DSI-RX too ?!

Is it something that you can share with us ? or your company sell the IP ??

 

Best regards

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jhallen
Observer
Observer
515 Views
Registered: ‎03-23-2017

It might be possible to share it as unsupported open source, I'm checking with the client.  But it will certainly take months before this could be possible.

 

wadelius
Participant
Participant
269 Views
Registered: ‎05-04-2018

Hi,

Do you have any update on this issue?

I think Im struggling with the same problem.

Did you change IP to something else?

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