MIPI PROTOCOLS WITH BROADCASTER

[marcos.bissiano]

Hi everyone!

I'm trying to connect a Test Pattern Generator (TPG) in a broadcaster which distribute the video stream to a MIPI CSI-2 Tx and a MIPI DSI. The DSI output pins are connected to a Inrevium board which are connected to a Display.

When I connect the TPG to broadcaster and the broadcaster to the DSI (without the CSI-2 Tx), my Display works right. But, If I connect the CSI in the Broadcaster too, my display stop working.

I use the Analyzer to watch the signal flow through the system. To DSI without CSI the waveform has the next format:



If I connect the CSI-2 Tx in broadcaster parallel to DSI, the waveform suffer a little change as follow:



The TVALID in the input of DSI is oscillating as CSI's TREADY, changing to low every 8 clock pulses. This behave is caused by CSI-2 Tx once it is the TVALID from it when used alone. I'm not shure if this may be the cause of my problem, but I believe it is changing the horizontal blanking time, and going out of the tolerancy of display.

Vivado: 2017.4
FPGA kit: KC705
Display image format: 1920x1200 RGB888
Display Horizontal Blanking: 120 [tolerance between 108 and 132]
s_axi_clk: 148.5 MHz
dphy_clk_200M: 200 MHz

My questions about the design are:

>Is normal to the TREADY of CSI present this behave or should it be continuous as DSI?

>Is possible to connect CSI-2 Tx and DSI parallel via broadcaster or another IP is necessary?

>Should the DSI and CSI-2 Tx work with the same line rate? (the outputs are to different devices)

Thank you for help

Regards!

Marcos

[karnanl]

Hello Marcos @marcos.bissiano

a) I am expecting MIPI CSI-2 TX tready to be continuously asserted during HS data transmittion.

If the IP deassert tready, please check for pixel under-run or buffer overflow (at Interrupt Status Register)

b)Could you please check PG260 Chapter 3, "Clocking" section ?  you can confirm if s_axis_aclk frequency you are using is okay or not.

c) I believe you can use AXI-Broadcaster IP as long as there is no big difference on the DSI/CSI-2 line rate.

1. BTW, what is the line-rate of your DSI TX & CSI-2 TX ?

2. What is the clock frequency of AXI4-Stream I/F ? 

Best regards

Leo

[marcos.bissiano]

Hi Leo, @karnanl

Thank you for the answer.

a) I am expecting MIPI CSI-2 TX tready to be continuously asserted during HS data transmition.

If the IP deassert tready, please check for pixel under-run or buffer overflow (at Interrupt Status Register)

I will implement it.

b)Could you please check PG260 Chapter 3, "Clocking" section ?  you can confirm if s_axis_aclk frequency you are using is okay or not.

I'm using a RGB888 standard with 4 lanes, pixel mode 1 and s_axis_clk = 148.5 MHz.

Only to confirm: The "pixel mode" is the same of "Pixels per beat" right?

c) I believe you can use AXI-Broadcaster IP as long as there is no big difference on the DSI/CSI-2 line rate.

I'm using DSI Tx with  1000 Mbps and CSI-2 Tx with 720 Mbps.

Best regards

Marcos

[karnanl]

Hello Marcos @marcos.bissiano

1. Yes. Pixel Mode = Pixel per beat.
2. If you are going to use 1 pixel per beat you will need 720x4/(24)x1.3=156MHz
Please let me know, if your CSI-2 TX still reporting buffer under-run with s_axis_aclk=156MHz.

Thanks & regards
Leo

Note:You may also need to recalculate the timing register for DSI TX if you change the s_axis_aclk.

[marcos.bissiano]

Hi Leo, @karnanl

I changed the s_axis_clk to 118.9 MHz (bellow the recommended) and works!

The TREADY stops the alternate behave. But, I'm thinking this oscillation isn't a problem, once my output signal seems right.

To verify it, I change my project to send an example present on PG260 in Clocking section: The RGB888 with 4 lanes and 4 pixels per beat. The result is the next:

As you can see, the TREADY is inconstant, but the output signal from MIPI still right.

It's possible the state machine from CSI-2 Tx is causing this oscillation? Should I accept this behave as common?

Thank you for the help.

Regards,

Marcos

[florentw · Accepted solution]

HI @marcos.bissiano,

The toggling on the tready signals is a common use case for video systems. It will mainly depends on your clock.

If your clock is facter than what it needs, then tready might toggling because you do not need data at this time.

If the output is fine, then you do not need to worry.

Regards,

[marcos.bissiano]

Hi @florentw!

Thank you for help. In this case, I think my problem is solved.

I'm very grateful to you and Leo (@karnanl) for the support.

Regards