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deltaxlx
Adventurer
Adventurer
1,450 Views
Registered: ‎05-27-2008

MIPI TX Subsystem minimum blanking period

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Hi,

I'm designing with the MIPI TX Subsystem core (Artix 7 baseboard) and I was wondering :

- Is there a minimum line blanking period?

- Is there a minimum frame blanking period?

Regards,

Benoit

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karnanl
Xilinx Employee
Xilinx Employee
1,361 Views
Registered: ‎03-30-2016

Hello Benoit @deltaxlx 

I am assuming that you are using MIPI CSI-2 TX Subsystem.

>- Is there a minimum line blanking period?
>- Is there a minimum frame blanking period?

MIPI CSI-2 spesification does not clarify any limitation/restriction on these blanking period min value.

but there are two things to be considered :
1. MIPI D-PHY has to changes mode from (HS mode)->(LP mode)->(HS mode), this HS/LP/HS down time can be considered as min line blanking period.
   ( See also MIPI D-PHY spec for details spec value )
DPHY_HS_LP_HS.png

    So, If you need to maximize bandwith utilization. You can try to:
    (a) Using continuous clock mode. Since this mode will reduce HS-LP-HS transition timing needed for clock lane.
    (b) Using higher line-rate setting.

2. I saw some MIPI receiver / MIPI deserializer devices that requires a spesific timing requirement
( for ex. Min blanking period, Frame start to packet header blanking time etc ), these timing requirement are beyond MIPI D-PHY spec scope.
Xilinx MIPI D-PHY RX IPs do not require additional timing requirement, but you may want to check if your MIPI receiver device requires a spesific timing.


Thanks & regards
Leo


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6 Replies
karnanl
Xilinx Employee
Xilinx Employee
1,362 Views
Registered: ‎03-30-2016

Hello Benoit @deltaxlx 

I am assuming that you are using MIPI CSI-2 TX Subsystem.

>- Is there a minimum line blanking period?
>- Is there a minimum frame blanking period?

MIPI CSI-2 spesification does not clarify any limitation/restriction on these blanking period min value.

but there are two things to be considered :
1. MIPI D-PHY has to changes mode from (HS mode)->(LP mode)->(HS mode), this HS/LP/HS down time can be considered as min line blanking period.
   ( See also MIPI D-PHY spec for details spec value )
DPHY_HS_LP_HS.png

    So, If you need to maximize bandwith utilization. You can try to:
    (a) Using continuous clock mode. Since this mode will reduce HS-LP-HS transition timing needed for clock lane.
    (b) Using higher line-rate setting.

2. I saw some MIPI receiver / MIPI deserializer devices that requires a spesific timing requirement
( for ex. Min blanking period, Frame start to packet header blanking time etc ), these timing requirement are beyond MIPI D-PHY spec scope.
Xilinx MIPI D-PHY RX IPs do not require additional timing requirement, but you may want to check if your MIPI receiver device requires a spesific timing.


Thanks & regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

deltaxlx
Adventurer
Adventurer
1,336 Views
Registered: ‎05-27-2008

Hi Leo,

Thanks a lot, it is now clear !

Benoit

steve_sandven
Newbie
Newbie
1,049 Views
Registered: ‎08-20-2020

How do I use a higher line rate setting?

Using Gear8 instead of Gear16?  or maybe fewer Tx Lanes on MIPI?

Thanks for any info

bingi
Newbie
Newbie
941 Views
Registered: ‎09-08-2020

So basically we need not consider any timings related to Front Porch, Back Porch, Sync duration we do in case of VGA?

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karnanl
Xilinx Employee
Xilinx Employee
926 Views
Registered: ‎03-30-2016

Hello @steve_sandven 

For a new question , I would suggest to post a new question on this Video board.

>How do I use a higher line rate setting?

You can set line-rate of MIPI CSI-2 TX using the IP GUI.
Please see also PG260.

>Using Gear8 instead of Gear16? or maybe fewer Tx Lanes on MIPI?

We do not use "Gear8/Gear16" term in D-PHY. That is a term/keyword for M-PHY.

Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
925 Views
Registered: ‎03-30-2016

Hello @bingi 

For a new question , I would suggest to post a new question on Video board.
This thread is for MIPI CSI-2 TX Subsystem as mentioned by deltaxlx.

>So basically we need not consider any timings related to Front Porch, Back Porch, Sync duration we do in case of VGA?

For MIPI CSI-2 TX Subsystem, yes.

If you are using MIPI DSI-TX, the timing requirement is different for each display.
So, you need to know the timing requirement for your display, and configure timing registers in MIPI DSI TX.  See also PG238 Chapter3 for a general guidelines to configure timing registers.


Regards
Leo


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Don’t forget to reply, kudo, and accept as solution.
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Versal Example Designs : LINK
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