MIPI design example simulation doesn't work!

[ifutritski]

MIPI design example simulation doesn't work! (Vivado 2019.1).

to reproduce:

1. create a design example project
2. run simulation

I've noticed these line in the TB:

parameter CLK_PERIOD = 5;

....

always #(CLK_PERIOD/2.0) clk_100MHz = ~clk_100MHz;

That looks wrong to me.

I've changed :

parameter CLK_PERIOD = 10;

Still not working - I never see anything come out our of MIPI core!

Any ideas?

[ifutritski]

After waiting for 1ms, I've got the output of MIPI TX core.

Should the clock period being fixed, then?

[karnanl]

Hello @ifutritski 

It should work with the default setting. Try to run the sim until 1,2ms.
If this is not working, please share the waveform screenshot.

Thanks
Leo

[aoifem]

Hi @ifutritski 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[ifutritski · Accepted solution]

1. IMO, the clock period should be fixed (see my original post)

2. I suggest to update the doc and clearly mention that 1.2ms wait is necessary

[karnanl]

Hello @ifutritski 

1. I cannot find the same signal in my MIPI D-PHY example design,
    but I think we do not have to change anything on the testbech to make MIPI D-PHY Example design run correctly.
2. MIPI D-PHY TX Initialization time (T_INIT) is set as 1ms as default, TX will have to drive LP-11 for a period longer than T_INIT, before TX start sending any HS data. 
    Perhaps we can add some notification in PG, I shall give your feedback to our developer team.
3. If you wish to speed-up MIPI D-PHY simulation , we do have an a parameter to do this. (CONFIG.C_EXAMPLE_SIMULATION)
    attached two tcl script. Please run both to compare the simulation speed.

Thanks & regards
Leo