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Observer
Observer
236 Views
Registered: ‎06-24-2015

MIPI example design Xcelium simulation not working Vivado 2019.2 and 2020.1

Hi,

I'm trying to simulate the example design for a MIPI CSI-2 Rx subsystem. We have a bought license for the MIPI Rx module and an evaluation license for the DSI module in order for the example design to elaborate.

 

My setup:

Linux, Ubuntu 18.04

Vivado 2019.2

Xcelium 19.03.s019

 

Exporting the simulation for the example design with the following settings:

Screenshot_68.png

and trying to run the simulation with the generated sh script, the first error that comes up is this one:

 

`include "xil_common_vip_macros.svh"
                                   |
xmvlog: *E,COFILX (/home/jsolis/deleteme/mipi_v19xc03_ed/mipi_csi2_rx_subsystem_0_ex/xcelium/srcs/xil_common_vip_pkg.sv,48|35): cannot open include file 'xil_common_vip_macros.svh'.

 

That's an easy fix, I copied the said file from Vivado's installation directory and then I got the following error:

 

use unisim.vcomponents.FDR;
          |
xmvhdl_p: *E,SELLIB (/home/jsolis/deleteme/mipi_v19xc03_ed/mipi_csi2_rx_subsystem_0_ex/xcelium/srcs/ip/design_1/lib_cdc_v1_0_2/lib_cdc_v1_0_rfs.vhd,60|10): unit (VCOMPONENTS) not found in library (UNISIM).

For this one I compiled the simulation libraries and added the -lib_map_path <sim_libraries_directory> option to the simulation script so it would use those instead of the ones automatically packed by Vivado's export utility.

I compiled the simulation libraries with this command:

 

compile_simlib -language verilog -dir ./sim_lib -simulator "xcelium" -simulator_exec_path "/home/tools/cadence/installs/XCELIUM1903/tools.lnx86/bin" -library "all" -family all -verbose

 

Now I'm getting this error.

 

 ) inst (
       |
xmelab: *E,CUVMUR (./srcs/ip/design_1/xil_defaultlib/bd_d92b_hsc_0.v,184|7): instance 'design_1_wrapper.design_1_i@design_1<module>.dsi_display_path@dsi_display_path_imp_K23T4O<module>.v_proc_ss_0@design_1_v_proc_ss_0_0<module>.inst@bd_d92b<module>.hsc@bd_d92b_hsc_0<module>.inst' of design unit 'bd_d92b_hsc_0_v_hscaler' is unresolved in 'xil_defaultlib.bd_d92b_hsc_0:v'.

 

This is getting a little bit frustrating, so I was wondering if this is a known issue or if I'm missing something.

 

I also tested this with a Vivado 2020.1 and Xcelium 19.09-s012 combination as that is the officially supported version of Xcelium for that Vivado release. Same results.

 

I'm attaching the simulator's log.

 

Jesus

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3 Replies
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Moderator
Moderator
227 Views
Registered: ‎11-09-2015

HI @jsolisa2e 

It is clearly written black on white in the PG232 that simulation is not supported for the MIPI RX CSI2 example design:

MIPI.JPG

Even if you fix the issues you are facing you will still not have anything working as there is not test bench to simulate the camera input...

You need to generate the example design of the MIPI CSI-2 TX if you want a simulation example for the MIPI RX subsystem


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
189 Views
Registered: ‎06-24-2015

Ok, I clearly oversaw that part of the documentation.

My main goal is not to have the example design simulate, but to make sure that the MIPI Rx subsystem compiles and elaborates with Xcelium. We have a test setup for our application (which works in hardware) and our own camera BFMs but we are having issues with the MIPI Rx controller module showing errors in Xcelium (protected source code, so no idea what the errors are).

I tried simulating the generated test bench for the MIPI Tx example design (PG260 does say a test bench is available), and I'm getting the exact same two first errors I had with the Rx subsystem example design: mising xil_common_vip_macros.svh and missing Vcomponents in UNISIM. After solving these, the last error is during elaboration, similar to the one I had on the Rx example design. Log attached.

Jesus

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Xilinx Employee
Xilinx Employee
139 Views
Registered: ‎03-30-2016

Hello @jsolisa2e 

I believe this is a simulation-library problem.

Have you compiled simulation libraries before running simulation ?
# If you do not know how to do this, please see also UG900 Chapter 2
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug900-vivado-logic-simulation.pdf

Thanks & regards
Leo