cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
656 Views
Registered: ‎07-31-2019

MIPI interface

Hi Xilinx Team,

I would like to know, The HP I/O banks only supports the MIPI lane interfaces in XAZU7EV zynq ultrascale+ MPSoC Device?  or if any other banks supports MIPI interface please provide the details..

Thank you!!!!

 

Regards,

Gajendiran A

Tags (1)
0 Kudos
7 Replies
karnanl
Xilinx Employee
Xilinx Employee
631 Views
Registered: ‎03-30-2016

Hello gajendiran.a@tataelxsi.co.in 

Yes, your understanding is correct.
For UltraScale+ devices you need to use HP IO banks to implement MIPI interface.

UltraScale+ datasheets and PG202 mention these:
MIPI_DPHY_is_only_supported_in_HP_bank.png
MIPI_DPHY_is_only_supported_in_HP_bank_PG202.png

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
548 Views
Registered: ‎07-31-2019

Hello,

Thanks for your update,
 

We are using xczu7evfbvb900 package in our design.

We have a DDR requirement where we need 64-bit DDR3 interface so I have used Bank 64/65/66 completely.  In addition to above requirement we need to interface two 4 lane CSI MIPI interface to this FPGA. And for MIPI I can’t use other than HP bank which is 64/65/66.

So my question would be can I use another bank other than 64/65/66 for interfacing DDR so that I can accommodate MIPI in one of this bank

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎03-30-2016

Hello gajendiran.a@tataelxsi.co.in 

I believe you cannot.
zu7ev-fbvb900 has 3 HP IO banks (Banks 64,65,66), you need to implement MIPI interface on HP IO banks.
Bank 47,48 does not support MIPI_DPHY_DCI IO standard.

HP_IO_bank_only_on54_65_66.png
Thanks
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
0 Kudos
505 Views
Registered: ‎07-31-2019

Hi Leo,

Thank you for the update...

Yes I can understand MIPI can be configured only in HP Bank (64,65,66). But for my case this banks  64,65,66 are assigned to PL DDR 64 bit completely...So is it possible to assign PL DDR to other bank (other than HP Bank).So that I can accommodate 2X 4 lane CSI MIPI in one of this bank(64,65,66).

Thank you !!!

 

0 Kudos
karnanl
Xilinx Employee
Xilinx Employee
500 Views
Registered: ‎03-30-2016

Hello gajendiran.a@tataelxsi.co.in 

>is it possible to assign PL DDR to other bank (other than HP Bank) ??

I don't think so. PL DDR also requires HP IO bank.

Thanks
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
396 Views
Registered: ‎07-31-2019

Hello Leo,

Thank you for your update...

Additional to this we have requirement of 64 bit DDR interface and 2X 4 MIPI interface. The 64 Bit DDR signal are mapped in HP bank(Bank 64,65&66) and 2X 4 MIPI signals also mapped in same HP bank (Bank 64). Here Bank 64 is used to DDR signal as well as MIPI signals and the bank 64 voltage is 1.2V both working in same voltage.

Is it possible to configure DDR and MIPI interface in the same Bank(Bank 64). Please confirm about electrical speciation combabilities and other specification.

 

Regards,

Gajendiran A

karnanl
Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎03-30-2016

Hello gajendiran.a@tataelxsi.co.in 

Implementing_MIPI_2x4lanes.png
Each HP IO bank of UltraScale+ devices consisted of 4 byte-groups.
You need to use 2 byte-groups to implement 2 instances of MIPI CSI-2 RX@4lanes. ( see above )
You can use the rest of the byte-groups for other purpose/IP.

For DDR4 I/O pins requirement please see : ug899 Chapter4. You need Memory Bank/Byte Planner for MIG IO planning. Please address your MIG related questions here : Memory Interfaces and NoC


Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
0 Kudos