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chance189
Participant
Participant
300 Views
Registered: ‎07-07-2019

Mipi CSI2 Pin Assignment Tab Not Displaying

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Hello all,

I am trying to instantiate the MIPI CSI-2 RX Subsystem Version 5.1, on Vivado 2021.1. My operating system is Ubuntu 18.04 LTS. I am targeting the xc7k160tffg676-2. From the guide (PG232) I was expecting an acceptable pinout to be found on the "Pin Assignment" tab. Is this no longer available in Vivado 2021.1?

Thanks for any help,

Chance

mipi_rx_gen.png
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karnanl
Xilinx Employee
Xilinx Employee
200 Views
Registered: ‎03-30-2016

Hello @chance189 

7-series LVDS IO support for 1500Mbps line-rate, but for some package it is limited to 1250Mbps.
PG202 Chapter 5 describes that

PG202_Chapter5_7series_line_rate.png

Please ensure that
1. Your design can meet 1400Mbps timing constraint.
2. Your system has a reasonable good signal integrity to transfer 1400Mbps line-rate MIPI D-PHY signal.

Kind regards
Leo


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3 Replies
watari
Professor
Professor
297 Views
Registered: ‎06-16-2013

Hi @chance189 

 

7 series doesn't support directly MIPI D PHY. So you can't use it.

Would you refer the following ?

 

https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf

 

Best regards,

chance189
Participant
Participant
289 Views
Registered: ‎07-07-2019

Hello @watari 

Thank you for your quick repy! I'm using the Meticom 20901 for a 4 lane Mipi D-PHY to LVDS. Due to CSI-2 being DDR, the max rate support should be 1400Mb/s as specified in table 17 of DS182, correct? So I'll just have to specify the pinouts manually then.

Thanks,

Chance

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karnanl
Xilinx Employee
Xilinx Employee
201 Views
Registered: ‎03-30-2016

Hello @chance189 

7-series LVDS IO support for 1500Mbps line-rate, but for some package it is limited to 1250Mbps.
PG202 Chapter 5 describes that

PG202_Chapter5_7series_line_rate.png

Please ensure that
1. Your design can meet 1400Mbps timing constraint.
2. Your system has a reasonable good signal integrity to transfer 1400Mbps line-rate MIPI D-PHY signal.

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post