cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Contributor
Contributor
434 Views
Registered: ‎07-28-2020

Mipi Rx subsystem to Zynq PS connection

Jump to solution

Hello everyone, I am trying to do some ISP on raw data received from Sensor via MIPI Rx Subsystem, before doing raw to RGB conversion.

All the designs/tutorials I have come across does demosaic/GammaLUT correction before dumping the data in PS DDR. My questions are:

1. Is it possible to transfer raw video/image data from PL(MIPI Rx subsystem) to PS DDR?

2. After doing ISP in PS, do some video processing in PL (like GammaLUT correction etc).

Can anyone help me by suggesting some study material/videos etc, or some tutorials/designs that something similar to this?

 

Regards

Nitin Kumar

0 Kudos
Reply
1 Solution

Accepted Solutions
Moderator
Moderator
310 Views
Registered: ‎10-04-2017

Hi @Nitin_Kumar,

The table is from UG934 page 9.

For more information on the Video Frame Buffer, see PG278.

 

If I want to transfer data over network using after demosaic/GammaLUT in PL, do I need to push data back into PS? If yes, how? otherwise how do i do it?

You will need to work with an interface IP to do this. I am not an expert in the network IPs, so I would push the question of "how to send a data stream over ethernet" to the ethernet forum.

I can say that using one of our TRD designs we do show this being done using Linux. My assumption is that if this can be done in Linux it can be done baremetal as well, but this is an assumption, please verify your options with the Ethernet team/documentation.

 

2020-08-26 07_32_20-Window.png

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

4 Replies
Moderator
Moderator
367 Views
Registered: ‎10-04-2017

Hi @Nitin_Kumar,

Can you confirm what you mean by ISP? Image signal processing?

1. Yes, it is possible to transfer "raw" video/image data from the PL to the PSDDR. To do this, set the Video Frame buffer to Y - only. As this is the same bus formatting as Bayer/Raw and the Video Frame Buffer supports Y10 this will work.
This example is for a baremetal application.

samk_1-1598390411693.png

 

2. Use the VFB to pull the data out of DDR and then push it into demosaic/GammaLUT as needed.

I don't currently know of any example designs for this, but the modifications should not be too difficult based on existing designs for VFB and MIPI designs.

Also, keep in mind that if you are doing processing-intensive ISP, you may need a special processor(GPU) to keep up with your Frames per Second as default processing systems are not specialized for Video applications.

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Contributor
Contributor
343 Views
Registered: ‎07-28-2020

Thanks @samk ,

1. Yes by ISP I do mean Image signal processing.

2. I am using Zynq Ultrascale+ MPSoC from Avnet, it has GPU inside. So, I guess that can be utilised for this purpose.

3. Can you share the source of this Table?

4. If I want to transfer data over network using after demosaic/GammaLUT in PL, do I need to push data back into PS? If yes, how? otherwise how do i do it?

Regards

Nitin Kumar

 

0 Kudos
Reply
Moderator
Moderator
311 Views
Registered: ‎10-04-2017

Hi @Nitin_Kumar,

The table is from UG934 page 9.

For more information on the Video Frame Buffer, see PG278.

 

If I want to transfer data over network using after demosaic/GammaLUT in PL, do I need to push data back into PS? If yes, how? otherwise how do i do it?

You will need to work with an interface IP to do this. I am not an expert in the network IPs, so I would push the question of "how to send a data stream over ethernet" to the ethernet forum.

I can say that using one of our TRD designs we do show this being done using Linux. My assumption is that if this can be done in Linux it can be done baremetal as well, but this is an assumption, please verify your options with the Ethernet team/documentation.

 

2020-08-26 07_32_20-Window.png

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

Contributor
Contributor
283 Views
Registered: ‎07-28-2020

Thanks @samk , for replying and all the information.

Regards

Nitin Kumar