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Visitor
Visitor
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Registered: ‎06-05-2020

Mipi csi2 RX tuser asserted cycle 1 and cycle 3

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I am having an issue with the TUSER signal being asserted in cycles 1 and 3. 

The path is MIPI csi-2 rx to broadcaster (other input has tready tied to 1).  The broadcaster feeds a register slice which feeds a 10-bit to 8-bit converting SSC which then feeds the VDMA.  

mipi to vdma block diagram.PNG

 

 

 

 

 

Vivado 2019.2
MIPI CSI-2 Rx Subsystem (4.1)

Here is a snapshot of an RTL simulation showing the duplicated tuser signal: 

TUSER cycle1 and cycle3.PNG

IF I override the tready signal from the VDMA -- hold it high -- then the VDMA will work EXCEPT for the first transfer where it will deassert tready from a few cycles and the tvalid data will be lost.  The result is that the first line of data is only 5-bytes shorter then it should be.  The rest of the lines see tready stay high and so are okay. 

If I DO NOT override the TREADY signal then the VDMA will not transfer data to the DDR.    

Based on previous posts I believe the behaviour I am seeing on TUSER(SOF) was supposed to be corrected in 2019.2.

Anyone see the same thing, or know how to fix this issue? 
Thanks, Malcolm

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Xilinx Employee
Xilinx Employee
120 Views
Registered: ‎03-30-2016

Re: Mipi csi2 RX tuser asserted cycle 1 and cycle 3

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Hello @malstew 

Unfortunately this issue still occurs in 2019.2 MIPI CSI-2 RX Subsystem.

Have you apply 2019.2 IP patch from AR#73100 ?
https://www.xilinx.com/support/answers/73100.html


Kind regards
Leo

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Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎03-30-2016

Re: Mipi csi2 RX tuser asserted cycle 1 and cycle 3

Jump to solution

Hello @malstew 

Unfortunately this issue still occurs in 2019.2 MIPI CSI-2 RX Subsystem.

Have you apply 2019.2 IP patch from AR#73100 ?
https://www.xilinx.com/support/answers/73100.html


Kind regards
Leo

View solution in original post

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