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thieuhiep
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Registered: ‎03-02-2010

Netlist is empty after trimming useless hardware

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Hi, all. I'm a newbie, I'm working with sysgen v8.2 and ISE8. A design my project with xilinx blocks and run simulations. My simulation run well, no error and the result is good. But when I generate the HDL code, it's has a problem, my FPGA kit is virtex4 and the problem is "Netlist is empty after trimming useless hardware". It's the first time I meet that kind of error, if anyone know how to solve this error, please share with me!

 

Thanks in advane!

Khoa.

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john.h
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Registered: ‎02-27-2010

If you've just been running simulations so far and wanted to check timing or placement of what you have so far, your problem may be common.

 

If your design doesn't come to outputs to demonstrate to the tool flow that you're actually using the partially-developed logic, there will be little to no design left.

 

If you have outputs from your logic so the dependence is obvious, the logic will remain.

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john.h
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Registered: ‎02-27-2010

If you've just been running simulations so far and wanted to check timing or placement of what you have so far, your problem may be common.

 

If your design doesn't come to outputs to demonstrate to the tool flow that you're actually using the partially-developed logic, there will be little to no design left.

 

If you have outputs from your logic so the dependence is obvious, the logic will remain.

View solution in original post

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thieuhiep
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Registered: ‎03-02-2010
Thanks you very much, I solved my problem!
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fruntxas
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Registered: ‎10-07-2009

john.h I fail to understand this solution you gave.

Could you be a bit more specific on the solution.

 

I'll attach the model I'm having trouble with as well which I related to the following topic:

http://forums.xilinx.com/t5/DSP-Tools/hwcosim-error-Dictionary-key-quot-empty-quot/m-p/193670#M4840

 

Thanks in advance,

 

Tiago
 

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john.h
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Registered: ‎02-27-2010
The forum topic you linked suggests a very different problem. The suggestion I made here last year was that a design that's in process and not completely hooked up is often optimized out of the design because the circuitry affects no outputs.
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fruntxas
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Registered: ‎10-07-2009
Thing is, if I change my compilation target I do get this error.

Oh well, appreciated anyway john
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ywu
Xilinx Employee
Xilinx Employee
4,668 Views
Registered: ‎11-28-2007

I replied to your other post below. Please try and stick to one thread:

 

http://forums.xilinx.com/t5/DSP-Tools/hwcosim-error-Dictionary-key-quot-empty-quot/m-p/194018#M4857 

 


@fruntxas wrote:
Thing is, if I change my compilation target I do get this error.

Oh well, appreciated anyway john



 

Cheers,
Jim
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