Hello all,
I am trying to build a simple DVI loopback on the ZCU102 and having some problems.
I have successfully built and tested the TRD video design and got working output. My setup is laptop -> ZCU102 RX-SS-> TX-SS -> Monitor, using Vivado 2018.3 and Petalinux 2018.3 on Ubuntu.
With my own Vivado design things do not work as well... My RX is working, and using the Xilinx EDID I see the right device, and am able to verify that video traffic goes in. The TX side does not seem to lock. Here's what I get for the log:
cat /sys/devices/platform/amba_pl\@0/a0020000.v_hdmi_tx_ss/vphy_log && cat /sys/devices/platform/amba_pl\@0/a0020000.v_hdmi_tx_ss/hdmi_log
VPHY log
------
GT init start
GT init done
TX frequency event
TX timer event
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
RX frequency event
RX timer event
RX DRU disable
CPLL reconfig done
GT RX reconfig start
GT RX reconfig done
CPLL lock
RX reset done
RX MMCM reconfig done
HDMI TX log
------
Initializing HDMI TX core....
Initializing VTC core....
Reset HDMI TX Subsystem....
TX cable is connected....
TX Stream Start
The TX Stream Up is missing... And the locked pin on the TX-SS is Low. However, the LOL signal from the Si5324 also goes low during Petalinux boot-up as it should...
My DTS is below:
&amba_pl {
/* 114.285MHz reference crystal (X9 on ZCU102 rev. D1) for Si5324 clock for HDMI */
/* IIC controller with Si5324 clock generator and DP159 retimer for HDMI TX */
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
IIC_Fabric: i2c@a0050000 {
status = "okay";
compatible = "xlnx,xps-iic-2.00.a";
/* interrupt-parent = <&axi_intc>; */
/* interrupts = <5 2>; */
interrupt-parent = <&gic>;
interrupts = <0 93 4>;
reg = <0x0 0xa0050000 0x0 0x10000>;
clocks = <&axi_lite_clk>;
#address-cells = <1>;
#size-cells = <0>;
/* Si5324 i2c clock generator */
si5324: clock-generator@68 {
status = "okay";
compatible = "silabs,si5324";
reg = <0x68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* input clock(s); the XTAL is hard-wired on the ZCU102 board */
clocks = <&refhdmi>;
clock-names = "xtal_0";
/* output clock */
clk0 {
reg = <0>;
/* HDMI TX reference clock output frequency */
clock-frequency = <27000000>;
};
};
/* DP159 exposes a virtual CCF clock. Upon .set_rate(), it adapts its retiming/driving behaviour */
dp159: hdmi-retimer@5e {
status = "okay";
compatible = "ti,dp159";
reg = <0x5e>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
};
};
axi_stream_clk: axi_stream_clk {
compatible = "fixed-factor-clock";
clocks = <&clk 71>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <6>;
};
axi_lite_clk: axi_lite_clk {
compatible = "fixed-factor-clock";
clocks = <&clk 71>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
};
&Video_PHY {
compatible = "xlnx,vid-phy-controller-2.2";
reg = <0x0 0xa0040000 0x0 0x10000>;
/* interrupts = <3 2>; */
/* interrupt-parent = <&axi_intc>; */
clocks = <&axi_lite_clk>, <&si570_2>;
clock-names = "axi-lite", "dru-clk";
xlnx,input-pixels-per-clock = <0x2>;
xlnx,nidru = <0x1>;
xlnx,nidru-refclk-sel = <0x4>;
xlnx,rx-no-of-channels = <0x3>;
xlnx,rx-pll-selection = <0x0>;
xlnx,rx-protocol = <0x1>;
xlnx,rx-refclk-sel = <0x1>;
xlnx,tx-no-of-channels = <0x3>;
xlnx,tx-pll-selection = <0x6>;
xlnx,tx-protocol = <0x1>;
xlnx,tx-refclk-sel = <0x0>;
xlnx,hdmi-fast-switch = <0x1>;
xlnx,transceiver-type = <0x5>;
xlnx,tx-buffer-bypass = <0x1>;
xlnx,transceiver-width = <0x2>;
vphy_lane0: vphy_lane@0 {
#phy-cells = <4>;
};
vphy_lane1: vphy_lane@1 {
#phy-cells = <4>;
};
vphy_lane2: vphy_lane@2 {
#phy-cells = <4>;
};
vphy_lane3: vphy_lane@3 {
#phy-cells = <4>;
};
};
&HDMI_TX {
compatible = "xlnx,v-hdmi-tx-ss-3.1";
reg = <0x0 0xa0020000 0x0 0x20000>;
reg-names = "hdmi-txss";
/* interrupt-parent = <&axi_intc>; */
/* interrupts = <4 2>; */
/* interrupt-names = "hdmitx"; */
interrupt-parent = <&gic>;
interrupts = <0 92 4>;
interrupt-names = "hdmitx", "hdcp1x", "hdcp1x-timer", "hdcp22", "hdcp22-timer";
clocks = <&axi_lite_clk>, <&axi_stream_clk>, <&si5324 0>, <&dp159>;
clock-names = "axi-lite", "video", "txref-clk", "retimer-clk";
phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
xlnx,input-pixels-per-clock = <2>;
xlnx,max-bits-per-component = <8>;
xlnx,output-fmt = "rgb";
};
&HDMI_RX {
compatible = "xlnx,v-hdmi-rx-ss-3.1";
reg = <0x0 0xa0000000 0x0 0x10000>;
reg-names = "hdmi-rxss";
/* interrupts = <2 2>; */
/* interrupt-parent = <&axi_intc>; */
/* interrupt-names = "hdmirx"; */
interrupt-names = "hdmirx";
interrupt-parent = <&gic>;
interrupts = <0 90 4>;
clocks = <&axi_lite_clk>, <&axi_stream_clk>;
clock-names = "axi-lite", "video";
phys = <&vphy_lane0 0 1 1 0>, <&vphy_lane1 0 1 1 0>, <&vphy_lane2 0 1 1 0>;
phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
xlnx,input-pixels-per-clock = <2>;
xlnx,edid-ram-size = <0x100>;
};The AXI4-S video goes from RX-SS to TX-SS. I'm using HDMI-to-DVI digital cables, so the ACR audio is disconnected as there's nothing there anyway.
Why is there no locked link on the TX side?
Thanks!
