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Contributor
Contributor
898 Views
Registered: ‎05-28-2018

No hd-sdi output.

Hi,

I am using spartan 6 fpga for Hd-Sdi video streaming, for this application am using spartan 6 GTP transiver and tripple rate sdi core, to make sure the external link i used ibert core, here loopback and near end is working and i checked pattern generation code which is also working fine.

but when i give HD video am not getting the output.

the below image shows when i connect HD video, i can see data is flowing in the core which was captured in chip scope.

My video resolution is 1280*720 and this is verified in chipscope am getting 1650*750 and in below image you can see that there is no payload data and it is showing payload valid id is one always.

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hdvideo.png
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Contributor
Contributor
881 Views
Registered: ‎05-28-2018

the below image shows the width of the TRS signal and EAV, i don't know whether data between TRS and EAV is proprer or not? 

trs.png
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Xilinx Employee
Xilinx Employee
810 Views
Registered: ‎08-01-2007

@hemanth_93I recommend you take a look at XAPP1076.  It is an example design that runs on the Spartan-6 SP605 demo board.  It not only contains the example design, but it also give some design advice that may help you in implementing and testing your Spartan-6 SDI design.

For the Spartan-6 FPGA Triple Rate SDI v1.0 (Rx) to work, the GT PLLs need to be locked on the reference clock.  The recommended reference clock for Spartan-6 SD-SDI is either 148.5MHz or 74.25MHz as documented in DS849 and XAPP1076.  Then once the PLLs are locked, then the IP will attempt to lock on the incoming stream.  If it can't lock on the incoming stream, then nothing else will work.  So you need to make sure that the Trile Rate SDI is locking to the proper mode.

If at all possible try to get an SP605 and the related AVB FMC (CTXIL671) card so that you can test out the example.  If you can't do that then at least review how the design is connected, and make sure to use the provided control logic as this is necessary to properly setup and control the GTs with the Triple Rate SDI IP.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Contributor
Contributor
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Registered: ‎05-28-2018

@chrisaras per my knowledge pll's were locked and here, transport family is also showing 1280x720 which is equal to 0001 in code this i saw in chip-scope and sometimes 1111

transport_lock is '1' from line number 1A to 1F(26th line to 31st line) i.e it became high when active pixel started.

this is in the attached picture.

locked.png
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