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ThomasG
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Registered: ‎03-18-2021

No more HDMI output on ZedBoard after adding VDMA

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Hello,

I am currently trying to use the ADV7511 on a ZedBoard for HDMI output. I could get the output of a Test Pattern Generator visible on my screen, but I want to replace the TPG with the VDMA IP. For now I placed the VDMA inbetween the TPG and AXI4-Stream to Video Out so that I could test it, but after that my screen remains black while it tells me "no signal detected", but not always. About 1 out of 10 times I will get my green screen from the TPG, but the other times not.

I have followed these tutorials for first getting the TPG output on screen:
https://forums.xilinx.com/t5/Video-and-Audio/Video-Series-19-Using-the-On-Board-HDMI-on-ZC702-Vivado-design/td-p/914989
https://forums.xilinx.com/t5/Video-and-Audio/Video-Series-20-Starting-with-SDK-and-configuring-the-ADV7511/m-p/917308
https://forums.xilinx.com/t5/Video-and-Audio/Video-Series-21-TPG-Application-on-ZC702/td-p/922324
After following these tutorials I have a block design with TPG, Subset Converter, VTC, AXI4-Stream to Video Out and an AXI IIC. I modified the design to output 1920x1080, instead of the 800x600 in the tutorial. The design works without problem and I get the expected green output on my screen via the ADV7511/HDMI. My next step was to expand this design with the VDMA IP, following the steps in this tutorial:
https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-24-Using-the-AXI-VDMA-in-Triple-Buffer-Mode/ba-p/938327
I put the VDMA inbetween the Subset Converter and the AXI4-Stream to Video Out, but after that I get no more output on my screen.
The documentation for AXI4-Stream to Video Out states that the timing mode should be "Master" when used with VDMA, so I changed it, but I still get no output.
I tried setting the VDMA Read Channel Fsync to "mm2s fsync" and connecting it to the VTC fsync_out, but I read in a post (https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/VDMA-Interrupt-not-serving-nothing-shows-on-screen/td-p/398715) that it is generally recommended to leave VDMA Read in freerun, so I changed it back.
This post states that it is recommended to drive the VDMA with a higher clock and use a FIFO for the data:
https://forums.xilinx.com/t5/Video-and-Audio/AXI-VDMA-different-clocks-for-input-and-output-streams/td-p/1047677
so I added the AXI data FIFO IP to my design, using a 148,5MHz clock for the VTC and Video Out and a 200MHz clock for the VDMA and TPG, but still my screen remained blank, so I removed the FIFO again.
I've also disconnected the vtg_ce and gen_clken pins from eachother, like said in this post:
https://forums.xilinx.com/t5/Video-and-Audio/VDMA-project/td-p/767851


When I look at other designs on this forum they are very similar to mine, so I am not really sure what I'm doing wrong. With only a TPG, VTC and AXI4 to Video Out I could see output on my screen, but after adding the VDMA it doesn't display anything. VDMA status registers say that there are no errors and that both channels are running, which surprises me considering there is no output. I feel like I've missed something obvious, but I admit that I'm not that experienced with the Zedboard yet. What am I doing wrong here?


I have attached my design as pdf.
Here are screenshots of the configuration for the video IPs:
AXI4-Stream to Video Out:
0 axi2vidout.PNG

VTC: frame sync position 0,0

1 vtc combi.PNG


VDMA:

3 vdma combi.PNG


Subset Converter:

5 subset.PNG

TPG:

6 tpg.PNG

Processor System Reset, AXI Interconnect and AXI SmartConnect blocks were generated with "Run Connection Automation", so I have left those blocks as is.


I have attached the PS C code that I'm using in one file as main.c. The code for the ADV7511 and TPG is the same as when I did not use the VDMA yet and the test pattern was still visible. The ADV7511 and TPG code is a modified version of the code found in the Video Series 19 to 21. The C code for the VDMA is an only slightly modified version of the code found in Video Series 24.

 

Using Vivado/SDK version 2019.1


Does anyone see where my fault is?

Regards,
Thomas

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Nikhil_Thapa
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Registered: ‎05-28-2020

Hi @ThomasG ,

I checked your BD and found that you were feeding pixel clock  to TPG, VDMA, VTC, AXI4-Stream to Video Out IP and HD_CLK.

You must have to feed pixel clock (148.5MHz for 1080p) to only following pins, such as, clk pin of VTC IP, vid_io_out_clk of AXI4-Stream to Video Out IP and HD_CLK. You need to feed AXI clock value to aclk pin of TPG, AXI4-Stream to Video Out IP and VDMA. AXI Clock should be greater than Pixel Clock.

I've also disconnected the vtg_ce and gen_clken pins from eachother

No, you must connect them. This connection is so important, by which AXI4-Stream to video out IP is able to synchronize video stream and its corresponding video timing. So, locked state can be achieved. 

You can use XSCT memory read/write command to check that data is written into memory or not. 

You can also use ILA to monitor the signal states.

You can also check the status, such as, Locked, Underflow and Overflow.

Hope this might help.

 

Thanks and Regards,

nikhil@logictronix.com
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Nikhil_Thapa
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Explorer
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Registered: ‎05-28-2020

Hi @ThomasG ,

I checked your BD and found that you were feeding pixel clock  to TPG, VDMA, VTC, AXI4-Stream to Video Out IP and HD_CLK.

You must have to feed pixel clock (148.5MHz for 1080p) to only following pins, such as, clk pin of VTC IP, vid_io_out_clk of AXI4-Stream to Video Out IP and HD_CLK. You need to feed AXI clock value to aclk pin of TPG, AXI4-Stream to Video Out IP and VDMA. AXI Clock should be greater than Pixel Clock.

I've also disconnected the vtg_ce and gen_clken pins from eachother

No, you must connect them. This connection is so important, by which AXI4-Stream to video out IP is able to synchronize video stream and its corresponding video timing. So, locked state can be achieved. 

You can use XSCT memory read/write command to check that data is written into memory or not. 

You can also use ILA to monitor the signal states.

You can also check the status, such as, Locked, Underflow and Overflow.

Hope this might help.

 

Thanks and Regards,

nikhil@logictronix.com
:::::Do not forget to Accept as solution, give Kudo and Share a post that you think is helpful:::::

View solution in original post

ThomasG
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Registered: ‎03-18-2021

Hello @Nikhil_Thapa,

Thank you for your reply

I did as you said and took a second clock for all the AXI clocks, but kept the pixel clock for the VTC and Video Out. iAlso connected vtg_ce and gen_clken again. The TPG output is now indeed back on my screen. I thought I had tried this in an earlier attempt, but I must have made a mistake then too. Reading the memory from XSCT shows that the memory is indeed being written to, so your solution worked. Thank you for helping and finding my problem!

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