07-20-2020 08:40 AM
Background: I have developed a custom video mixer which receives input video stream data from a TPG(Rainbow color). After performing blending operation it sends out data from its AXIS Master interface. This is connected to the input AXIS Slave interface of the AXI4S to Video Out IP. The frame dimension is 1280x720. I have verified the control signals along with data are coming out properly from my video mixer AXIS Master interface.
The AXI4S to video out IP is configured in slave mode and connected to VTC which is configured as a "Generator". It is also controlled through SW using an AXI4 Lite Slave CTRL interface.
Problem: I don't see any timing signals on the output side of the AXI4S to video interface and also nothing appears on the display port. vid_data, vid_active_video, vid_vblank etc i.e. the Video Output signals are all in-active or '0'. Locked signal is also low and I see status register as x"3EF008F".
PFA the snippet of ila capture of the video out signals, along with the BD snippet.
07-20-2020 10:21 PM
Hello @vishal_cg ,
Please check, whether the locked signal (Output port of AXI4S to Video Out IP) is active high. If not, then please refer the debug synopsis addressed in Table C-1 of PG044.
Also, I noticed that the input clken signal of VTC IP was left unconnected. Please check the clken input port addressed in VTC IP. Because, detector and generator clock enables are associated with this clock enable as shown in the attached images. Those Images are addressed as Figure 2-2 and Figure 2-3 in PG016.
Kindly let me know these details.
07-21-2020 01:26 AM
Thanks for the suggestions. PFB my observations:
1. Locked signal was low with my previous setup as well as after making the changes you suggested. Status register now reports x"00C0000" value. (I had already looked into the debug synopsis of PG044).
2. "I noticed that the input clken signal of VTC IP was left unconnected" -- I have connected this to the vtg_ce port of the axi4s to vid out IP similar to gen_clken. Still no timing signals generated by the axi4s to vid out IP. Previous observation was with the clken port of the vtc left unconnected, the vtc was generating the timing signals. But after connecting it these outputs from the vtc are '0'. You can verify this with the attached snippet of the ILA I have sent before.
Few other inputs about the design I would like to mention here are:
1. The AXI clock is 100Mhz driven by pl_clk0(fabric clock from PS) and the Video clock is 74.250Mhz driven out by a MMCM as seen in the BD attached. Input to this MMCM is pl_clk0.
2. When I remove my custom video mixer logic and connect the vtpg directly to the axi4s to video out ip, I see it working, with the expected color pattern getting displayed on the DP.
3. I see proper SOF and EOL signal coming out of my AXIS Master IF of the custom video mixer IP. Snippet attached for perusal.
07-22-2020 04:01 AM
I have gone through the "Video Beginner Series 8". As seen in my simulation I see the AXI4S to Vid out IP status register bit(3) is set to '1'. As suggested by you @florentw in one of your reply to another user, I have taken care of setting the VTC to the desired resolution in my case 1280x720(720p). I still didn't see the IP getting locked.
The vtpg, vtc, v_axi4s_to_vid_out and my custom video mixer IP receives the same clock(ap_clk = 300Mhz).
vtpg- 4096x4096, 1PPC, datawidth=8, background & foreground all selected.
vtc- 4096x4096, frame syncs= 1, Enable Generation, Generation options selected. Defaulf/Constant: 720p.
axi4s_to_vid_out: 1PPC, RGB, 8, 8, FIFO depth= 1024, Common, Slave, Hysteresis Level=12.
I have attached a snippet of my sim along with BD, please suggest what needs to be done in this case.
07-22-2020 05:32 AM - edited 07-22-2020 05:36 AM
I suggest you to turn off "Vertical Blank Generation" and "Horizontal Blank Generation", if your design didn't require blank signals.
Or, modify blank setting on vtc.
Also, make sure whether pixel clock is proper frequency or not, too.
07-22-2020 05:38 AM
Hi @watari ,
Thank you for the suggestion. Any particular reason for pointing out the blank signals? I will disable them in the IP settings and check. If had to be modified what settings should I use?
07-22-2020 06:59 AM
Hi @watari ,
After disabling the blank generation from the vtc IP settings, I now see the axi4s to vid out IP video output signals(vid_active_video, vid_vsync, vid_hsync) toggling. But the locked signal is still low and there is no video data output. Am not getting any trigger on the underflow & overflow in ILA.
The pixel clock is correct and works fine, I have verified this by removing my custom IP and connecting the vtpg directly to the axi4s to vid out IP. I see the expected result on the display port.
I have attached the ILA screenshots for your perusal. Please suggest.
07-22-2020 12:45 PM
What is your target frame rate ?
Also make sure proper pixel clock frequency from this answer and your target resolution.
And make sure input floating on axi4 stream to video output module and fix it, too.
07-24-2020 03:05 AM
Hi @watari ,
Thank you for the suggestions. I have made sure input floating on axi4s to vid out is fixed.
As per the zcu102 user guide I found this- "DisplayPort interface-implements a DisplayPort source-only interface with video resolution up to 4K x 2K-30 (300 MHz pixel rate)."
My current setup is frame dimension = 1280x720(720p), AXI clock= 100MHz, this clock also goes to my custom IP, vtpg, axi4s_to_vid_out IP. I have a video clock of 74.250 Mhz connected to vtc(configured for 720p), vid_io_out_clk of axi4s to vid out ip(Independent mode) and to dp_video_in_clk on the Zynq US+ MPSOC.
I am able to achieve lock in simulation with my custom IP added to it also data is seen on the bus vid_data. PFA the snippet of the same for your perusal.
I am moving forward as per your suggestions. I will keep you posted.
07-24-2020 03:14 AM
Hi @vishal_cg ,
If you think your BD is correct and working, then I do recommend reviewing your SDK code properly. Because, I believe that you have done coding for configuring video mixer stream parameters, such as, framerate, timing, pixel per clock and so on. And one thing we must not forget that the VTC must generate the timing information, based on what video mode we set in the video mixer. Otherwise, we will be far from getting locked signal, even though video mixer is working.
I hope, it might help.
07-24-2020 03:46 AM
Yes I have taken care of the video mode in SDK. The video mode for VTC and video mixer are configured for the same 1280x720 frame.
I have one doubt, is it mandatory that the VTC and my custom IP should work on the same clock. In my current setup the vtc is operating on DP video clock of 74.250 Mhz and custom ip works on 100 Mhz.
07-25-2020 03:29 AM
I confirmed your clock constraints and performance on axi4 stream.
It seems performance issue on axi4 stream. There is a few margin to transfer stream.
So, I suggest you to change frequency of axi4 stream from 100[MHz] to ex. 125[MHz].
Would you try it ?
07-25-2020 11:57 PM
Hi @watari ,
Firstly thank you for looking into my design in detail and for pointing out the performance issue. I have checked the design by changing the axi clock to 125 Mhz as suggested by you but still no 'lock'.
I have attached the BD and ila snippet for your perusal. I also tried increasing the axi frequency to 150 Mhz but the result remains same as it was for 125 Mhz. I see status = '1' since start and even after trying out different scenario's. How can one deal with this issue of "VTG EOL LEADING"?
07-26-2020 02:37 PM
Would you fix input floating issue in Video Timing Controller ?
You should fix "Input floating" at whole design.
Logic synthesis tool, like Vivado, generates wrong netlist by this input floating issue.
07-27-2020 03:46 AM
How can one deal with this issue of "VTG EOL LEADING"?
Have you really read my Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP? The answer is in it:
If bit 3 is ‘1’, it indicates VTG EOL (End Of Line) Leading. This means that the EOL signal (hsync) from the Video Timing Generator happens before the EOL signal from the AXI4-Stream (tlast). In other words, the horizontal size configured in the VTG is smaller than the horizontal size coming on the AXI4-Interface
The issue you probably have is that you video mixer is not producing the correct amount of pixel, this is why you can never lock with it while it is locking with the TPG.
07-27-2020 04:00 AM
Hi @florentw ,
I have gone through Series 8 before posting my question on the forum. I am actually wondering why this is happening, because as mentioned by you about the horizontal size configuration, I have checked the size configured in the VTG and the no. of pixels getting generated on the axi stream interface of the video mixer along with the total # of lines. They look OK in the ILA. Anyways I will double check on this and let you know with some snippets from the ILA.
07-27-2020 04:04 AM
Create a small HDL logic to count the number of pixels per lines out of your IP. I would not be surprised if the number is not as expected
07-27-2020 04:09 AM
Use the same counter to check the TPG to make sure you counter is correct
07-28-2020 01:24 AM
Hi @florentw ,
Please find attached ILA snippets for the hdl pixel and line counters for AXIS slave & master interfaces. Please note in AXIS Slave IF it counts pixels from 0 to 1279(write_pointer) and in AXIS Master IF it is sending the pixels out from 1 to 1280(pixel_counter) for lines 0 to 719(tlast_counter_reg). Let me know if anything looks wrong here.
07-28-2020 01:46 AM
It is hard to see with only a small part of the waveform. For example one thing that you would need to check is that the counter is not counting if tready = 0.
Did you do the same test with the TPG IP? Are you getting the same to check that the counter is valid?
07-28-2020 02:33 AM
Hi @florentw ,
Yes, it is not counting when tready is low. You can confirm that in the attached ILA snippet. tready signal color is yellow for both the axis slave/master interfaces.
I will count the total # of pixels coming from TPG whenever the TPG IP tvalid is high.
My axis slave side receives data from TPG. I have a fifo which stores one line(1280 pixels) and de-asserts tready when the fifo is full, back pressure to TPG. The design sink is always ready(axis_tready) to accept the tdata until the FIFO is not filled with # of input words(1280).
07-28-2020 02:51 AM
Then if you think the number of pixel matches between the TPG and your IP I am not sure what is the issue. But as the TPG is working, it has to be a subtile differences you have to find ...
07-28-2020 04:39 AM
Hi @florentw ,
Please find the ILA snippet. I have added a counter signal to count the # of pixels coming from TPG. It is sending 1282 pixels but I will store only 1280(one line) by asserting tready low as described in my last post.