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santhapurharsha
Visitor
Visitor
4,004 Views
Registered: ‎07-28-2011

Normalized sampling period of FIR Compiler v5.0

Hi ,

How can we set the Normalized sampling frequency of the block?

 

I am designing a small design, in which i am using FIR Compiler v5.0 .

 

I used two FIR filters, in one of which i used decimation(125) application. After decimation(125), i applied the output through another FIR filter.

 

Then i tried to genarate the verilog code from the design using system generator.

 

Then i got an error as :

 

==================================================================================================

This block requires that normalized sampling period on din port and that of the block are equal for the block to be adapted to "Expose clock ports" or " Hybrid-DCM" netlisting.

The normalized sampling period of the input port was found to be : 125.00

The normalized sampling period of the block was found to be : 1.00

==================================================================================================

 

 

Can anyone please help me/tell me .. how to change the normalized sampling period value? (even if manually)

 

Thanks

Sriharsha S

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chrisar
Xilinx Employee
Xilinx Employee
3,982 Views
Registered: ‎08-01-2007

You can look t the norimized priods by changing the block view from the System Genertor Token.

it looks like you are trying to do a systm where you want to control the clocks, most likely due to the large rate change.  I haven't seen the error before, but if you are trying to specify the sampilng rate for the block, that might be what is causing the conflict.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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santhapurharsha
Visitor
Visitor
3,974 Views
Registered: ‎07-28-2011

Hi Chris,

 

I am attaching you the model file...

 

I am using 12.4 ISE, with 2010a Matlab..

 

Please check the model, with FIR architecture as Transpose Multiply Accumulate.. and run the simulation.

Later , also please try to generate the Verilog code from the model.

 

 

 Also please generate the Netlist IN  " Hybrid-DCM " MODE...

You might get the same error.

 

Thanks

Sriharsha S

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chrisar
Xilinx Employee
Xilinx Employee
3,932 Views
Registered: ‎08-01-2007

If you want to see the normailzed frequencies you will need to open the SysGen token and under the General tab you can change the display to normized frequencies.  You can then find out what SysGen thinks is the normalized frequncy for your blocks and they try to meet the requirements needed to generate the Hybrid DCM wrapper.

 

I think that part of the problem is that some blocks must always run at the system rate when using the Hyrid DCM wrapper.  You may want to consult the System Generator for DSP User Guide on this.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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