cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
shree9_7
Participant
Participant
612 Views
Registered: ‎11-15-2019

Not able to generate Test patterns for Native Video stream !

Jump to solution

Hello Support Team,

I am struggling to generate the Test Pattern signals to test the DisplayPort TX subsystem design. The design is based on the reference design from below link.

https://github.com/laurivosandi/hdl/blob/master/zynq/xilinx-test-pattern-generator.rst

I modified the video test pattern generator example as per the design but when I flashed the code on board and checked the waveforms using ILA then there was no signals. I have also attched the code snippet for your reference.

int driverInit()
{
	int status;

	vtc_Config = XVtc_LookupConfig(XPAR_V_TC_0_DEVICE_ID);
	if(vtc_Config == NULL)
	{
		xil_printf("ERR:: VTC device not found\r\n");
		return(XST_DEVICE_NOT_FOUND);
	}
	status = XVtc_CfgInitialize(&vtc, vtc_Config, vtc_Config->BaseAddress);
	if(status != XST_SUCCESS)
	{
		xil_printf("ERR:: VTC Initialization failed %d\r\n", status);
		return(XST_FAILURE);
	}

	tpg1_Config = XV_tpg_LookupConfig(XPAR_V_TPG_0_DEVICE_ID);
	if(tpg1_Config == NULL)
	{
		xil_printf("ERR:: TPG device not found\r\n");
		return(XST_DEVICE_NOT_FOUND);
	}
	status = XV_tpg_CfgInitialize(&tpg1, tpg1_Config, tpg1_Config->BaseAddress);
	if(status != XST_SUCCESS)
	{
		xil_printf("ERR:: TPG Initialization failed %d\r\n", status);
		return(XST_FAILURE);
	}

	return(XST_SUCCESS);
}

void videoIpConfig(XVidC_VideoMode videoMode)
{
	XVidC_VideoTiming const *timing = XVidC_GetTimingInfo(videoMode);
	u16 PixelsPerClk;
	int status;

	status = XV_tpg_IsReady(&tpg1);
	printf("Status %u \n\r", (unsigned int) status);
	status = XV_tpg_IsIdle(&tpg1);
	printf("Status %u \n\r", (unsigned int) status);
	XV_tpg_Set_height(&tpg1, timing->VActive);
	XV_tpg_Set_width(&tpg1, timing->HActive);
	XV_tpg_Set_colorFormat(&tpg1, 0);
	XV_tpg_Set_bckgndId(&tpg1, XTPG_BKGND_COLOR_BARS);
	XV_tpg_Set_ovrlayId(&tpg1, 0);
	XV_tpg_Set_enableInput(&tpg1, 1);
	XV_tpg_Set_passthruStartX(&tpg1, 0);
	XV_tpg_Set_passthruStartY(&tpg1, 0);
	XV_tpg_Set_passthruEndX(&tpg1, timing->HActive);
	XV_tpg_Set_passthruEndY(&tpg1, timing->VActive);

	XV_tpg_EnableAutoRestart(&tpg1);
	XV_tpg_WriteReg(tpg1_Config->BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, 0x81);

	PixelsPerClk = tpg1.Config.PixPerClk;

	vtc_timing.HActiveVideo  = timing->HActive/PixelsPerClk;
	vtc_timing.HFrontPorch   = timing->HFrontPorch/PixelsPerClk;
	vtc_timing.HSyncWidth    = timing->HSyncWidth/PixelsPerClk;
	vtc_timing.HBackPorch    = timing->HBackPorch/PixelsPerClk;
	vtc_timing.HSyncPolarity = timing->HSyncPolarity;
	vtc_timing.VActiveVideo  = timing->VActive;
	vtc_timing.V0FrontPorch  = timing->F0PVFrontPorch;
	vtc_timing.V0SyncWidth   = timing->F0PVSyncWidth;
	vtc_timing.V0BackPorch   = timing->F0PVBackPorch;
	vtc_timing.VSyncPolarity = timing->VSyncPolarity;
	XVtc_SetGeneratorTiming(&vtc, &vtc_timing);
	XVtc_Enable(&vtc);
	XVtc_EnableGenerator(&vtc);
	XVtc_RegUpdateEnable(&vtc);
}

Also I have some doubts about the design which are as below:

1) Is it required to use the reconfigurable Clock wizard in the design ?

2) If I don't use the reconfigurable Clock wizard in the design then do I need to use the videoClockConfig() function in my code ?

Thanks in advance,

Regards,

Shree9_7

 

 

0 Kudos
1 Solution

Accepted Solutions
florentw
Moderator
Moderator
534 Views
Registered: ‎11-09-2015

@shree9_7 wrote:

I modified the video test pattern generator example as per the design but when I flashed the code on board and checked the waveforms using ILA then there was no signals. I have also attched the code snippet for your reference.

[Florent] - I wrote some blog articles as part of my video series.

One is showing the TPG working in simulation

Video Beginner Series 4: Simulation with the Xilinx TPG IP

and the other is showing the TPG working in HW

Video Series 21: TPG Application on ZC702

If you have no data out, you might want to make sure the tready from the downstream IP is high. This is something I shared in my Video Series 31 – Debugging a Video System using an ILA

1) Is it required to use the reconfigurable Clock wizard in the design ?

[Florent] - Well, if you are planning to do a native interface, yes you need to adapt the pixel clock. Video Series 22: Supporting multiple video resolutions on ZC702 HDMI might be a good read for you. Again as per your previous topic, it would probably be much easier for you to use the AXI4-Stream interface of the DP SS IP

2) If I don't use the reconfigurable Clock wizard in the design then do I need to use the videoClockConfig() function in my code ?

[Florent]  - I guess not I haven't read the code

 

PS: Could you kindly close your previous topic by marking it as solved as you have now this current topic opened?

Thanks in advance,

Regards,

Shree9_7

 

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

0 Kudos
2 Replies
florentw
Moderator
Moderator
535 Views
Registered: ‎11-09-2015

@shree9_7 wrote:

I modified the video test pattern generator example as per the design but when I flashed the code on board and checked the waveforms using ILA then there was no signals. I have also attched the code snippet for your reference.

[Florent] - I wrote some blog articles as part of my video series.

One is showing the TPG working in simulation

Video Beginner Series 4: Simulation with the Xilinx TPG IP

and the other is showing the TPG working in HW

Video Series 21: TPG Application on ZC702

If you have no data out, you might want to make sure the tready from the downstream IP is high. This is something I shared in my Video Series 31 – Debugging a Video System using an ILA

1) Is it required to use the reconfigurable Clock wizard in the design ?

[Florent] - Well, if you are planning to do a native interface, yes you need to adapt the pixel clock. Video Series 22: Supporting multiple video resolutions on ZC702 HDMI might be a good read for you. Again as per your previous topic, it would probably be much easier for you to use the AXI4-Stream interface of the DP SS IP

2) If I don't use the reconfigurable Clock wizard in the design then do I need to use the videoClockConfig() function in my code ?

[Florent]  - I guess not I haven't read the code

 

PS: Could you kindly close your previous topic by marking it as solved as you have now this current topic opened?

Thanks in advance,

Regards,

Shree9_7

 

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

0 Kudos
samk
Moderator
Moderator
481 Views
Registered: ‎10-04-2017

Hi @shree9_7,

 

 

 Was florentw's response able to answer yoru questions?

If your question is answered or your issue is solved, please kindly mark the response which helped find a solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply to the thread giving more information on your current status.

Thanks and Regards,

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
0 Kudos