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Observer
Observer
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Registered: ‎06-25-2019

Not able to get any output when using Video Processing Subsystem in Vivado 2019.2.

Hi,

We are trying to create a custom design with VPSS for upscaling 1920x1080@60 to 3840x2160@60. The Video Processing Subsystem(VPSS) is configured in scaler only mode.  The number of Samples per clock is 4. The maximum data width is 8.  The scaler is configured for a clock frequency of 150MHz. Since the number of samples per clock is 4 we believe the input streaming clock frequency is sufficient. We have attached screenshots of the other configurations.

We probed the internal signals of VPSS and have attached screenshots below. It seems the horizontal scaler is back pressuring the other blocks. TREADY signal from 'horizontal scaler' to 'axis FIFO' block is only asserted for a very small duration(not even for one line). At some later point, TREADY gets asserted but gets de-asserted quickly. This behaviour seems to continue but TREADY doesn't get asserted long enough to transfer incoming data. What would be the possible reasons for this? Moreover, it seems even though hscalar is not receiving any input, at the output 'TVALID' and 'TLAST' toggles. There were 1621 TLAST pulses before the VPSS stops giving any output.

What is the reason for this and how can we overcome this issue? Is there a way to view the HLS codes which were used to create VPSS?

The VPSS configured in stream mode.  We are using Vivado 2019.2 and VPSS v2.2

Driver

Since we were not able to get the V4l2 media-ctl interface up using the V4L2 based driver(Path 1), we copied the exact register writing sequence from the V4L2 based driver to the xlnx driver(Path 2) having debug interface.

Path 1. https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/drivers/media/platform/xilinx/xilinx-vpss-scaler.c

Path 2. https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/drivers/gpu/drm/xlnx/xlnx_scaler.c 

We are testing with the Path 2 driver having the exact register writing sequence( including phase setting and coefficient loading) as that of the Path 1 driver just without the V4L2 interface.

We have verified the Width_in, Height_in, Format_in, Width_out, Height_out, Format_out, Pixel rate, Line rate registers by reading the registers after VPSS configuration with Path 2 driver.

How can we overcome this issue and bringup the VPSS?

Thanks in advance. 

axis at different internal blocks of VPSS_2.PNG
axis at different internal blocks of VPSS_3.PNG
axis at different internal blocks of VPSS_4.PNG
vpss_config_1_v2_2.png
vpss_config_2_v2_2.png
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Moderator
Moderator
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Registered: ‎11-21-2018

Hi @shahan.a 

There is an issue with the vpss v2.2 in scalar only mode. 

Can you please check if the following fixes your issue?

https://www.xilinx.com/support/answers/73687.html

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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