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Observer
Observer
4,198 Views
Registered: ‎04-25-2013

On USAGE of HARDWARE Cosimulation

hi

 

I am trying to do hardware co simulation for the the convolution code i have written in VHDL using black box in Xilinx System Generator tool i am getting error During XFLOW Process due the routing restricions and available resources as i am using spartan 3e starter kit can any one help me in this regard i am attaching my files to this post.

 

thanks and regards

teja

Thanks and Regards
Teja
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5 Replies
Observer
Observer
4,196 Views
Registered: ‎04-25-2013

Errors reported while X flow process are as follows..........

 

 

Phase 1.1  Initial Placement Analysis


ERROR:Place:665 - The design has 2 block-RAM components of which 1 block-RAM


   components require the adjacent multiplier site  to remain empty. This is


   because certain input pins of adjacent block-RAM and multiplier sites share


   routing ressources. In addition, the design has 20 multiplier components.


   Therefore, the design would require a total of 21 multiplier sites on the


   device. The current device has only 20 multiplier sites.





Phase 1.1  Initial Placement Analysis (Checksum:a3ef15d4) REAL time: 4 secs





ERROR:Pack:1654 - The timing-driven placement phase encountered an error.





Mapping completed.


See MAP report file "jtagcosim_top_map.mrp" for details.


Problem encountered during the packing phase.


Thanks and Regards
Teja
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Observer
Observer
4,179 Views
Registered: ‎04-25-2013

When using nexys 2 board xc3s1200e am getting similar error

 

Phase 1.1 Initial Placement Analysis
ERROR:Place:665 - The design has 2 block-RAM components of which 1 block-RAM
components require the adjacent multiplier site to remain empty. This is
because certain input pins of adjacent block-RAM and multiplier sites share
routing ressources. In addition, the design has 28 multiplier components.
Therefore, the design would require a total of 29 multiplier sites on the
device. The current device has only 28 multiplier sites.

Phase 1.1 Initial Placement Analysis (Checksum:83a2a052) REAL time: 5 secs

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file "jtagcosim_top_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors : 2
Number of warnings : 0
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...

Thanks and Regards
Teja
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Xilinx Employee
Xilinx Employee
4,169 Views
Registered: ‎11-28-2007

The error message is telling you that there are too many multipliers in your design because 1 multiplier is not usable due to BRAM/MULT sharing routing resource. You will need to reduce the MULT usage in your model.

 


@tejakr2002 wrote:

Errors reported while X flow process are as follows..........

 

 

Phase 1.1  Initial Placement Analysis


ERROR:Place:665 - The design has 2 block-RAM components of which 1 block-RAM


   components require the adjacent multiplier site  to remain empty. This is


   because certain input pins of adjacent block-RAM and multiplier sites share


   routing ressources. In addition, the design has 20 multiplier components.


   Therefore, the design would require a total of 21 multiplier sites on the


   device. The current device has only 20 multiplier sites.





Phase 1.1  Initial Placement Analysis (Checksum:a3ef15d4) REAL time: 4 secs





ERROR:Pack:1654 - The timing-driven placement phase encountered an error.





Mapping completed.


See MAP report file "jtagcosim_top_map.mrp" for details.


Problem encountered during the packing phase.





Cheers,
Jim
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Observer
Observer
4,166 Views
Registered: ‎04-25-2013

How can i reduce multiplier usage in my code how to limit the synhesizer

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Teja
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Observer
Observer
4,165 Views
Registered: ‎04-25-2013

How to make this constraint in system generator tool can i actually control the number of multipliers in synthesis part of hardware co simulation

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Teja
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