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Contributor
Contributor
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Registered: ‎08-09-2020

PG230: video phy controller

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can the register  work because they have been tied 0 inside RTL code?

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ha4456 

Do you have any updates on this? Did my reply clarify things?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Hi @ha4456 

You are not mentioning which configuration of the Video PHY you used. But anyway, I just think you are looking at the incorrect section of the code. I have tried with the Video PHY configured for HDMI TX and RX. 

Checking where the gtwizard is instantiated, I can see that these signals coming from the registers are connected and used. Example with GTTXRESET:

gt_vphy.PNG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ha4456 

Do you have any updates on this? Did my reply clarify things?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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