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shahan.a
Participant
Participant
330 Views
Registered: ‎06-25-2019

PL to PS Interrupt requirements

Hi,

I am working on a design where I have to encode 2k@60 video data received from an SDI RX port using VCU. I am using VDMA for transferring SDI RX data to PSDDR. To synchronize writing and reading I am using a custom RTL to create an Interrupt that gets triggered when the VDMA S2MM Frame pointer value changes. Once the Interrupt is triggered the PS will reset the interrupt through an AXI Lite interface and it will start reading the frame from PS DDR.

The VDMA S2MM Frame pointer after gray to binary conversion is stored in a register. PS reads this register to identify s2mm frame pointer location.

While testing and watching output video frame by frame it seems the write and read goes out of synchronization after 30-40 seconds. But after 10-20 sec synchronization returns. Then it remains synchronized for another 30-40 seconds, which is again followed by synchronization error.

I believe this could be because of interrupt. I used a simple custom RTL for generating the interrupt I have attached the RTL used. The clk frequency is 100MHz.

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always @ (posedge clk) begin
        s2mm_frm_in_d1<=s2mm_frm_ptr_in;
        s2mm_frm_in_d2<=s2mm_frm_in_d1;
end
always @ (posedge clk) begin
        if(!rst_n) begin
            usr_irq_out<=0 ;
        end else begin
            if ((s2mm_frm_in_d1!=s2mm_frm_in_d2) && irq_en) begin
                usr_irq_out <= 1;
            end else if (isr_done || !irq_en) begin
                usr_irq_out <= 0;
            end else begin
                usr_irq_out <= usr_irq_out;
            end
        end
end
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 Is my RTL correct for generating an interrupt? Or Should I create the interrupt at the PS core clock frequency? 

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kvasantr
Moderator
Moderator
241 Views
Registered: ‎04-12-2017

Hello @shahan.a 

Have you already looked at our VCU TRD designs for reference?

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841711/Zynq+UltraScale+MPSoC+VCU+TRD

we have never used VDMA IP for VCU applications and don't recommend them to use as well. We always recommend to use framebuffer read/write pair for capture and display path.

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shahan.a
Participant
Participant
202 Views
Registered: ‎06-25-2019

Hi @kvasantr,

Thanks for the reply.

Is there any particular reason for using Frame buffer Write IP rather than VDMA?

We got the above observation when we used the main profile of VCU for encoding. One more interesting observation we had is when we used the base profile for encoding, the encoded video didn't seem to have any issues at least for 8 mins.

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kvasantr
Moderator
Moderator
144 Views
Registered: ‎04-12-2017

Hello @shahan.a 

VDMA  IP doesn't provide support for semi planar video formats which is must for Xilinx VCU core.

Following answer record summarizes everything that you should know about both the DMA IPs and there usage.

https://www.xilinx.com/support/answers/72543.html

 

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