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michelle
Explorer
Explorer
971 Views
Registered: ‎09-29-2018

PRBS7 transmission

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Hi,

I'm trying to send PRBS7 test pattern and found the link https://forums.xilinx.com/t5/Video/Displayport-tx-compliance-inter-pair-skew/m-p/972492#M25198

If I don't test the inter-lane skew, is it OK not to enable TX buffer bypass?

I was using existing ZCU102 DPTX and after DP link is established and video is out, I sent the following command:

Write to DPRX through Aux write, write DPCD reg 0x102 with value 0x2C

Then do the following:

1. XDptx_WriteReg(dp->xdp->Config.BaseAddr, XDP_TX_TRAINING_PATTERN_SET, 0);
2. XDptx_WriteReg(dp->xdp->Config.BaseAddr, XDP_TX_SCRAMBLING_DISABLE, 1);
3. XVphy_WriteReg(dp->vphy.Config.BaseAddr, XVPHY_TX_CONTROL_REG, 0x01010101);
4. XDptx_WriteReg(dp->xdp->Config.BaseAddr, XDP_TX_LINK_QUAL_PATTERN_SET, 3);

However, the DP link lock is lost. 

What's the proper procedure of turning on PRBS7 test pattern?

 

Thanks and Regards,

Michelle

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florentw
Moderator
Moderator
695 Views
Registered: ‎11-09-2015

Hi @michelle

I believe the PRBS7 pattern needs to be set during link training to evaluate the quality at a specific speed.

Usually the link training is controlled through the driver. 

Thus you would need to modify the drivers to control the training. If the link is already trained, I do not believe you can set the PRBS7 patern

Regards 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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11 Replies
watari
Professor
Professor
949 Views
Registered: ‎06-16-2013

Hi @michelle 

 

FYI.

 

> What's the proper procedure of turning on PRBS7 test pattern?

 

- Increase size of eye pattern.

- Improve compatibility.

- Improve toletance of SSC.

 

and so on.

 

Best regards,

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michelle
Explorer
Explorer
944 Views
Registered: ‎09-29-2018

@watari 

To clarify my question, 

1. Is it OK not to enable TX buffer bypass ( to confirm that DP link failure is not due to the bypass setting)

2. What's the proper steps to enable PRBS7? or What's wrong in my previous setting that link is unlocked.

Thanks and Regards,

Michelle

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watari
Professor
Professor
941 Views
Registered: ‎06-16-2013

Hi @michelle 

 

Here is my answer.

 

1. It depends on your target application and considering compatibility of your system.

2. It depends on your design and your system environment. (Include PCB schematic, sink device and so on.)

 

As you know, it is hard to replay what you want to know without detail information...

 

Best regards,

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michelle
Explorer
Explorer
938 Views
Registered: ‎09-29-2018

@watari 

I'm using ZCU102 and DP1.4 TXSS example design. 

Based on this, what's the proper steps to turn on PRBS7?

Thanks!

Regards,

Michelle

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watari
Professor
Professor
921 Views
Registered: ‎06-16-2013

Hi @michelle 

 

Um, it's hard to reply it for me by English...

 

As you know, PRBS is pseudo randome binary sequence.

In high speed signal world, "transition time" and "valid window" are very important.

 

As you know, transition time is related with signal level of previous few cycle.

I recommend to observe this signal as eye pattern by high speed oscilloscope, if you are interesting it.

 

And, it is worst case, when you use PRBS7 as this input pattern.

 

So, this is very important to increase area of eye pattern.

 

>Based on this, what's the proper steps to turn on PRBS7?

 

I'm not sure.

But document of VESA DP or Xilinx's source code or datasheet for this procedure are very useful for you.

 

Best regards,

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florentw
Moderator
Moderator
864 Views
Registered: ‎11-09-2015

Hi @michelle 

As mentioned in the topic you refered (https://forums.xilinx.com/t5/Video/Displayport-tx-compliance-inter-pair-skew/td-p/972492/page/3), in DP1.4, the Inter-pair skew test is optional and is unlikely to be a reason for non-interoperability. So no, we do not recommend to set TX buffer bypass with DP1.4.

Then why do you need to turn the PRBS7 pattern manually? Are you try to do a test equipment?

I believe the steps mentioned in the other forums topic are correct. How are you evaluating if is is working or not?

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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michelle
Explorer
Explorer
828 Views
Registered: ‎09-29-2018

@florentw 

Thanks for your confirmation. The reason we tried to run PRBS7 is to check the link quality. We plan to read the DPCD register through AUX to get error count after sending PRBS7 pattern. However, after writing to DPRX DPCD to notify PRBS7 pattern will be sent and then I followed exactly as the referred link, then I found the DP link is no longer locked.

Regards,

Michelle

florentw
Moderator
Moderator
807 Views
Registered: ‎11-09-2015

Hi @michelle 

The PRBS7 is part of the training. So if you are already trained, you are not supposed to send it.

For the previous link, this was done during the training phase, as a testing equipment would do.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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michelle
Explorer
Explorer
779 Views
Registered: ‎09-29-2018

@florentw 

I am still confused. PRBS7 is link quality pattern, not training pattern.

When running link training, there's specific test pattern to run, for clock recovery or channel equalization.

If to run PRBS7 pattern, the training patter is off, and link quality pattern is set to PRBS7.

I don't understand how to use PRBS7 as a training pattern to get link locked, that's why I first established DP link and then turn on PRBS7 pattern.

Let me know.

Thanks and Regards,

Michelle

florentw
Moderator
Moderator
696 Views
Registered: ‎11-09-2015

Hi @michelle

I believe the PRBS7 pattern needs to be set during link training to evaluate the quality at a specific speed.

Usually the link training is controlled through the driver. 

Thus you would need to modify the drivers to control the training. If the link is already trained, I do not believe you can set the PRBS7 patern

Regards 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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aoifem
Moderator
Moderator
608 Views
Registered: ‎11-21-2018

Hi @michelle 

 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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