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bly3145
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Registered: ‎11-30-2018

PS DisplayPort maximum resolution of 1024x768

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Hi all,

We are using an Ultrazed EV SOM + Carrier dev board with OSL flow software using Yocto 2.6 + Xilinx 2019.1. When connected to a 1080p DP monitor, the maximum resolution shown by modetest was 1024x768.

For comparison, I used an SD card to load the pre-built BOOT.BIN and image.ub files from the Xilinx maxtrix multiply example (2019.1 version). This also shows a maximum resolution of 1024x768 from modetest. The modetest output below is from the prebuilt version (not our software).

The monitor is a DELL P2419H with 1920x1080 native resolution and DisplayPort version 1.2. It is connected with a DP cable (no adapters). The same monitor displays in native resolution when connected to a laptop.

Should I expect this monitor to function in native resolution (1920x1080) when connected to the Ultrazed board? Is there anything that can be done to get it to function at the native resolution?

Thanks for your help!

root@uz7ev-evcc-2019-1:~# modetest -M xlnx
Encoders:
id crtc type possible crtcs possible clones
38 37 TMDS 0x00000001 0x00000000

Connectors:
id encoder status name size (mm) modes encoders
39 38 connected DP-1 530x300 7 38
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
1024x768 75 1024 1040 1136 1312 768 769 772 800 78750 flags: phsync, pvsync; type: driver
1024x768 60 1024 1048 1184 1344 768 771 777 806 65000 flags: nhsync, nvsync; type: driver
800x600 75 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync; type: driver
800x600 60 800 840 968 1056 600 601 605 628 40000 flags: phsync, pvsync; type: driver
640x480 75 640 656 720 840 480 481 484 500 31500 flags: nhsync, nvsync; type: driver
640x480 60 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver
720x400 70 720 738 846 900 400 412 414 449 28320 flags: nhsync, pvsync; type: driver
props:
1 EDID:
flags: immutable blob
blobs:

value:
00ffffffffffff0010acd9d0545a5330
2e1d0104a5351e783a0565a756529c27
0f5054a54b00714f8180a9c0d1c00101
010101010101023a801871382d40582c
45000f282100001e000000ff00474d47
584639424530535a540a000000fc0044
454c4c205032343139480a20000000fd
00384c1e5311010a202020202020005b
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 0
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
6 non-desktop:
flags: immutable range
values: 0 1
value: 0
19 CRTC_ID:
flags: object
value: 37
40 sync:
flags: range
values: 0 1
value: 0
41 bpc:
flags: enum
enums: 6BPC=6 8BPC=8 10BPC=10 12BPC=12
value: 8

CRTCs:
id fb pos size
37 44 (0,0) (1024x768)
1024x768 75 1024 1040 1136 1312 768 769 772 800 78750 flags: phsync, pvsync; type: driver
props:
20 ACTIVE:
flags: range
values: 0 1
value: 1
21 MODE_ID:
flags: blob
blobs:

value:
9e330100000410047004200500000003
01030403200300004b00000005000000
40000000313032347837363800000000
00000000000000000000000000000000
00000000
18 OUT_FENCE_PTR:
flags: range
values: 0 18446744073709551615
value: 0
30 output_color:
flags: enum
enums: rgb=0 ycrcb444=1 ycrcb422=2 yonly=3
value: 0
31 bg_c0:
flags: range
values: 0 4095
value: 0
32 bg_c1:
flags: range
values: 0 4095
value: 0
33 bg_c2:
flags: range
values: 0 4095
value: 0

Planes:
id crtc fb CRTC x,y x,y gamma size possible crtcs
35 0 0 0,0 0,0 0 0x00000001
formats: VYUY UYVY YUYV YVYU YU16 YV16 YU24 YV24 NV16 NV61 GREY Y10 BG24 RG24 XB24 XR24 XB30 XR30 YU12 YV12 NV12 NV21 XV15 XV20
props:
7 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 0
16 FB_ID:
flags: object
value: 0
17 IN_FENCE_FD:
flags: signed range
values: -1 2147483647
value: -1
19 CRTC_ID:
flags: object
value: 0
12 CRTC_X:
flags: signed range
values: -2147483648 2147483647
value: 0
13 CRTC_Y:
flags: signed range
values: -2147483648 2147483647
value: 0
14 CRTC_W:
flags: range
values: 0 2147483647
value: 0
15 CRTC_H:
flags: range
values: 0 2147483647
value: 0
8 SRC_X:
flags: range
values: 0 4294967295
value: 0
9 SRC_Y:
flags: range
values: 0 4294967295
value: 0
10 SRC_W:
flags: range
values: 0 4294967295
value: 0
11 SRC_H:
flags: range
values: 0 4294967295
value: 0
34 tpg:
flags: range
values: 0 1
value: 0
36 37 44 0,0 0,0 0 0x00000001
formats: AB24 AR24 RA24 BA24 BG24 RG24 RA15 BA15 RA12 BA12 RG16 BG16
props:
7 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 1
16 FB_ID:
flags: object
value: 44
17 IN_FENCE_FD:
flags: signed range
values: -1 2147483647
value: -1
19 CRTC_ID:
flags: object
value: 37
12 CRTC_X:
flags: signed range
values: -2147483648 2147483647
value: 0
13 CRTC_Y:
flags: signed range
values: -2147483648 2147483647
value: 0
14 CRTC_W:
flags: range
values: 0 2147483647
value: 1024
15 CRTC_H:
flags: range
values: 0 2147483647
value: 768
8 SRC_X:
flags: range
values: 0 4294967295
value: 0
9 SRC_Y:
flags: range
values: 0 4294967295
value: 0
10 SRC_W:
flags: range
values: 0 4294967295
value: 67108864
11 SRC_H:
flags: range
values: 0 4294967295
value: 50331648
28 alpha:
flags: range
values: 0 255
value: 255
29 g_alpha_en:
flags: range
values: 0 1
value: 1

Frame buffers:
id size pitch

 

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Accepted Solutions
florentw
Moderator
Moderator
1,018 Views
Registered: ‎11-09-2015

Hi @bly3145 

Great. Glad you found a way of achieving higher resolution.

I should stop assuming most boards would use the max number of lanes :(.

Yes for a monitor supporting max 1080p you are most likely to have a line rate limited to 2.7Gbps as this is what was done with DP1.1 specification (even if the monitor is DP1.2 compliant, it is only optional to support 5.4Gbps).

As you got your issue resolved, could you kindly close the thread by marking a reply as accepted solution? I guess this thread might be useful for other members

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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1,292 Views
Registered: ‎11-09-2015

HI @bly3145 

It might be that the displayport link is not able to train at high line rates. Did you try different cables? Are you using a certified DP1.2 mini-DP to DP cable?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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bly3145
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Registered: ‎11-30-2018

Thanks. The cables I tried are 6 ft, male to male standard connector DisplayPort cables marked like this:

Cable 1: 012DD-HTN1-990

Cable 2: HOTRUN E246588

I don't know if they are certified. I believe cable 1 was included with the Dell monitor.

I have also tried a Samsung CF391 monitor (1920x1080 native) and the resolution obtained was 1280x800.

If training failure is the cause of low resolution, are there any corrective actions other than cable replacement?

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florentw
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Registered: ‎11-09-2015

HI @bly3145 


I have also tried a Samsung CF391 monitor (1920x1080 native) and the resolution obtained was 1280x800.

If training failure is the cause of low resolution, are there any corrective actions other than cable replacement?


Well to do a corrective action we need to understand what is the issue really. But as the Ultrazed board is known to work I would think the cable would be the first thing to test.

With the GPU, are you also using DP?

I assume you do not have a DP aux analyzer? (I am asking just in case)

Can you check the value of the following registers:

DP.JPG

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
bly3145
Visitor
Visitor
1,195 Views
Registered: ‎11-30-2018

Hi Florent,

I haven't tried to use the GPU yet, I'm just booting the board and checking available resolutions.

Unfortunately I don't have a DP aux analyzer.

Today I tried a new cable having this description: "KabelDirekt – 8K DisplayPort Cable Version 1.4 (VESA Certified, Supports 8K 60 Hz, 4K 120 Hz, HBR3, DSC, HDR10, DP8K) – 3 feet". Again, no adapters, no HDMI, standard DP connectors both ends. 

This cable had no effect on the resolution - it still has a maximum of 1024x768.

Here are the register values:

root@uz7ev-evcc-2019-1:~# devmem 0xFD4A0000 32
0x0000000A
root@uz7ev-evcc-2019-1:~# devmem 0xFD4A0004 32
0x00000001
root@uz7ev-evcc-2019-1:~# devmem 0xFD4A0008 32
0x00000001

--- Thanks, Bruce

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watari
Professor
Professor
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Registered: ‎06-16-2013

Hi @bly3145 

 

According your register value, your system output DP packet as 2.7[Gbps] x 1 [lane].

So, maximum resolution on PS Display Port is 1024x768.

 

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

BTW, I confirmed the following schematic.

 

http://zedboard.org/sites/default/files/documentations/PRJ-US3CAR-1-01-02-Schematic-Prints.pdf

 

It seems that there is only one lane as main stream for Display Port.

Also, it might need to take care signal quality to achieve FHD (1920x1080@60p) resolution.

 

So, I just ask you.

How long is your DP cable ?

I guess you should use DP cable as short as possible to achieve 5.4[Gbps] x 1[lane] (FHD (1920x1080@60p)).

 

Would you try it ?

 

Best regards,

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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

HI @bly3145 

As @watari mentioned, there is only one lane trained and only at 2.7Gbps, this is why you cannot get the maximum resolution.

  • Are you sure you enabled both lanes in the ZynqMP configuration (Dual upper or Lower)?
  • What is the Carrier dev board? Is it from AVNET as well? Maybe check with your FAE if it is possible to test another one just to make sure this is not an issue with it.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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bly3145
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Registered: ‎11-30-2018

Hi Florent,

After looking at the schematic for the carrier card, it appears to have only one lane connected (which can operate up to 5.4 Gbps). We're guessing the monitors we used supported multiple lanes at 2.7 Gbps. The intersection of these resulted in one lane at 2.7 Gbps. The solution was to find a monitor which is able to support a higher speed on one lane. Currently I'm using an HP Z24x which is able to provide 1920x1080 resolution. Thanks to you and @watari for your help.

florentw
Moderator
Moderator
1,019 Views
Registered: ‎11-09-2015

Hi @bly3145 

Great. Glad you found a way of achieving higher resolution.

I should stop assuming most boards would use the max number of lanes :(.

Yes for a monitor supporting max 1080p you are most likely to have a line rate limited to 2.7Gbps as this is what was done with DP1.1 specification (even if the monitor is DP1.2 compliant, it is only optional to support 5.4Gbps).

As you got your issue resolved, could you kindly close the thread by marking a reply as accepted solution? I guess this thread might be useful for other members

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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