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Participant
Participant
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Registered: ‎01-09-2018

Pixels per clock

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I have a UHDSDI TX/RX subsystem AND a HDMI TX/RX subsystem in my design.

The problem is the SDI only supports 1 pixel/clk and the HDMI supports only 2 or 4 pixels/clk. The I/O to these is in the AXI domain. Is there a way to convert AXI stream video back and forth between various PPCs? I need to have a common PPC in my design. Also, the SDI seems to support only 10bits/component. To save resources, I want 8 bits/component. Is there a way to truncate the AXI stream video components to/from the SDI IP? This IP does not have access to the natve, everything is in AXI.

I am using Vivado 2017.3, targeting a Zynq EV US+ MPSOC.

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Participant
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Registered: ‎01-09-2018

OK thanks I will accept as solution

View solution in original post

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @bmoore,

 

To convert from 1 ppc to 2/4ppc -> use the VDMA

 

To convert from 10 bits to 8 bits you should be able to use the AXI subset converter. It is also easy to write your own logic in verilog or vhdl as it is direct connection with unconnected signals.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant
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Registered: ‎01-09-2018

How would I use the VDMA to do that? Do I now need an external memory buffer and a MIG? Is there an example design somewhere? How much memory would I need? I would like to avoid external memory if possible. Would an AXI stream fifo do the same thing?

 

As for the 10 to 8 bit conversion, I assume you mean editing the TDATA remap string in the subset convertor.

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Moderator
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Registered: ‎11-09-2015

Hi @bmoore,

 

How would I use the VDMA to do that?

> Different size for the input and output

 

Do I now need an external memory buffer and a MIG?

> It would be better with external memory but you should be able to do it with internal memory (but this would be a bit waste)

 

Is there an example design somewhere?

> I am not sure about this...but I don't think so

 

How much memory would I need?

> Enough to store a complete frame

 

I would like to avoid external memory if possible. Would an AXI stream fifo do the same thing?

> Yes you might be able to also use an AXI FIFO

 

As for the 10 to 8 bit conversion, I assume you mean editing the TDATA remap string in the subset convertor.

> Yes it might work

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant
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Registered: ‎01-09-2018

Florent, the UHDSDI subsystem video AXI TDATA is a 64 bit word. Do you know how the pixel data is mapped into that word, or where I can find that info? I need to know where the 2 lsbs of each component lie so I can truncate/pad the data in the subset convertor, or if I write code to do that.

 

Regarding the 2PPC to 1PPC conversion, using 1 frame's worth of memory just for that is a non-starter for me. I might use the display port RX subsystem instead of the HDMI. I think the displayport offers 1PPC, unlike the HDMI, right?

 

Regards, Brian

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Moderator
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Registered: ‎11-09-2015

Hi @bmoore,

 

From my understanding, the msb of the 64 bits word are unused to give the 60 bits word, then when you move from 10 bit to 8 bit it should be the same as explained in the TPG PG:

TPG.PNG

 

I think the displayport offers 1PPC, unlike the HDMI, right?

Yes you can do 1 ppc with Displayport

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant
Participant
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Registered: ‎01-09-2018

OK thanks I will accept as solution

View solution in original post

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Observer
Observer
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Registered: ‎06-08-2018

so how do you solve the issue of one to two pixels per clock  ?

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @tom.ymwang,

 

Please do not post question on someone else's topic. Please create a new topic on the Video Board (Click new message). To get more chance to get an answer quickly, you might want to follow the Recommendations for creating a topic in the Video board.

 

I am closing this topic as it is already solved.

 

Thank you for your understanding,

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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