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Visitor
Visitor
5,175 Views
Registered: ‎05-20-2008

Possible to reset a vector state variable in Mcode?

Hi all.

 

I would like to ask whether it's possible to reset a vector state variable to 0 in Sysgen Mcode, e.g. with 128 elements?

 

If not, is there any good solution to deal with it, except using 128 cycles to assign every element to 0?

 

Thanks a lot!

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Xilinx Employee
Xilinx Employee
5,163 Views
Registered: ‎08-02-2007

Are you talking about using something like Z = zeros([1 128])? This could probably be used to 'reset' a variable.
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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Visitor
Visitor
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Registered: ‎05-20-2008

Hi rjduran. Thanks for your reply.

But I tried to use the method that you mentioned. It didn't work.

A small example code in Mcode is:

***************************

 

function Dout=VecRst_test(rst)

 

persistent vec_var, vec_var= xl_state(zeros(1,128),{xlUnsigned, 9, 0},128);

persistent n, n=xl_state(0,{xlUnsigned, 7, 0});

 

if rst

vec_var=zeros(1,128);

n=0;

 

else

    if
n<64

       vec_var(n)=n;

    else

       vec_var(n)=0;

    end

end

Dout=vec_var(n);

n=n+1;

*****************

What I want to do is to use a vector state variable with 128 elements in Mcode that can be update with some condition, and can be reset to 0 if rst signal comes.

 

If I want to simulate this Mcode block in Sysgen, there is always an error message:

"Error("VecRst_test.m"): line 7:5 Persistent variable vec_var cannot be re-assigned with a vector".

 

I can understand that it's not an easy task in hardware. If tool maps this vector state variable into a RAM. In order to reset all the elements of this vector state variable to 0, we need to reset 128 addresses in RAM parallelly. I found an old post from Mr.Peter Alfke related to this question.

******************

Question:

My Vertex 4 design uses BRAM as a buffer to accumulate data before writing it to external DRAM.  The BRAM is hand instantiated in the RTL code.  The user guide seems to indicate that it is only possible to initialize BRAM contents during configuration of the fpga device.  There are situations where my controller would like to return the BRAM contents to it's initial value during normal operation without resetting the entire design.  Is this possible?  How can I do it? 

 

Answer: Roland, RAMs generally have no parallel data reset, since that would require costly parallel access to every bit cell, and additional routing complexity. No DRAM and no large SRAM has a data reset function, for that reason.
The world has learned to live with this restriction.
You can, however reset the address register in many designs.
 
Peter Alfke
Director, Applications Engineering,
Xilinx
San Jose

*************************** 

But I don't know whether there is any new solution or improvement. Since my project has very critical timing restriction, I really don't want to spend 128 cycles to reset all the 128 elements. Hope this fool method is not the only solution.:-)

Message Edited by luckhuting on 06-30-2008 12:54 AM
Message Edited by luckhuting on 06-30-2008 12:57 AM
Message Edited by luckhuting on 06-30-2008 12:59 AM
Message Edited by luckhuting on 07-02-2008 12:28 AM
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