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jonathanfei
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Registered: ‎02-10-2017

Problem enabling hidden parameter in VDMA

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Hi guys, I am trying to debug my VDMA by using the FRMPTR_STS (24h) register.
I learned that to do this, I need to enable it by using a command(s) in the TCL console as per page 61 of the pg020 document on VDMA 6.2:

pg020.PNG

Capture6.PNG

 

I have tried the following command: 

set_property -dict [list CONFIG.C_ENABLE_DEBUG_INFO_12 {1}] [get_bd_cells VdmaGeneratorTest_frame_rate_vdma_0]

(VdmaGeneratorTest_frame_rate_vdma_0 is the name of my component)

 

and I get this error:

ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

I have also tried the second suggestion from the document:

 

 

set_property -dict [list CONFIG.c_enable_debug_all {1}] [get_ips VdmaGeneratorTest_frame_rate_vdma_0]

and in the console I see it returns 0 which I have no idea what it means but it does not seem to give an error: 

 

 

return0.PNG

I then synthesize, run implementation and generate bitstream but the FRMPTR_STS register still does not work/does not give any info. 


Does anyone know what I am doing wrong here?

 

 

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florentw
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Registered: ‎11-09-2015

Hi @jonathanfei,

 

What does the tcl console returns with the follwonig command:

get_bd_cells VdmaGeneratorTest_frame_rate_vdma_0

If there is nothing, then you need to find the correct name of the IP. You will probably need to use something like

get_bd_cells -hierachical VdmaGeneratorTest_frame_rate_vdma_0

or

get_bd_cells *VdmaGeneratorTest_frame_rate_vdma_0

Hope that helps,

 

regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @jonathanfei,

 

What does the tcl console returns with the follwonig command:

get_bd_cells VdmaGeneratorTest_frame_rate_vdma_0

If there is nothing, then you need to find the correct name of the IP. You will probably need to use something like

get_bd_cells -hierachical VdmaGeneratorTest_frame_rate_vdma_0

or

get_bd_cells *VdmaGeneratorTest_frame_rate_vdma_0

Hope that helps,

 

regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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jonathanfei
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Registered: ‎02-10-2017

Hey @florentw, good to see you again (you helped me last time as well with a video generator problem I was having). 

 

Ran the commands you mentioned but they all throw errors:

capture7.PNG

So there seems to be a problem with the name of the IP, but every way I check it I don't think I am writing it wrong. This is the VDMA in question from the ip integrator: 

Capture9.PNG

 

And when I double click I can see the component name which I assume is what I need? In this case: VdmaGeneratorTest_frame_rate_vdma_0. Could this be a bug? Would it help to just delete this VDMA and add a new one?Capture8.PNG

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florentw
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Registered: ‎11-09-2015

Hi @jonathanfei,

 

Happy to see that you are glad to hear from me ;-)

 

No I don't think this is a bug. You just need to correctly refer it to find it.

 

Assuming you have only one VDMA in your BD you can try

get_bd_cells *vdma*

 

If your IP is in a hierarchy, you need to add the -hierarchical option -> I missed the "r" in my last response. That is why you have an error

get_bd_cells -hierarchical *vdma*

 

If it still do not find it, please try

get_bd_cells -hierarchical -filter {NAME=~"*VDMA*"}

 

Hope that helps,

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
jonathanfei
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Registered: ‎02-10-2017

@florentw

 

Yes, indeed it was in a hierarchy. This does not throw error anymore:

set_property -dict [list CONFIG.C_ENABLE_DEBUG_INFO_12 {1}] [get_bd_cells /DUT_wrapper/frame_rate_vdma]

But when I generate the bitstream and upload it to the FPGA and program it, the FRMPTR_STS register only shows its default value of 0. No idea why...

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florentw
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Registered: ‎11-09-2015

Hi @jonathanfei,

 

Quick check:

1. Did you run again the command after checking that you were selecting the IP (get_ips axi_vdma_xyz returns your IP):

 

   set_property -dict [list CONFIG.param_name {1}] [get_ips axi_vdma_xyz]

 

2. same for the command

set_property -dict [list CONFIG.c_enable_all {1}] [get_ips axi_vdma_xyz]

3. Did you regenerate the BD output product?

 

4. Do you see data transferred to/from the VDMA?

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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jonathanfei
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Registered: ‎02-10-2017

@florentw

I think the problem is on my end. I found out that the new bit file I am generating is not being uploaded to the device. I will mark your answer as the solution. Thanks!

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jonathanfei
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Update: I am using Vivado 2015.2, there was a bug with the design runs, several runs were not being run. To solve this just go to the Design Runs tab and manually select the modules that are causing problems, right click and reset them. Then synthesize your design normally. This fixed the issue for me.