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1,194 Views
Registered: ‎12-25-2018

Problem on getting SDI link1 to work on ZCU102 board (Import SDI TX subsystem from ZCU106). Vivado v2018.3

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Hi,

I have implemented UHD-SDI transmitter subsystem on ZCU102 v1.1 board. (Import the design from ZCU106 example) The example design is working for SDI link 0. I have modified the design that the PICXO FRACXO REF clock come from internal clock, rather than the SDI receiver clock. I am able to transmit 12G SDI output and receive 12G SDI input by looping back the signal using SFP0 case.(by using optical transceiver module on SFP0)

But when I configure the UHD-SDI GT to include SDI link 1, I am not able to get TXOUTCLK from SDI link 1(by probing the TXOUTCLK). The SDI link 0 continue to work in 12G.

I only got one reference clock that is connected to GTREFCLK0 and is connected to inf_0_qpll0_refclk_in and inf_0_qpll1_refclk_in.

I configure the uhdsdi_gt_ctl.v as show below. Is the setting correct for SDI link1?? It is working for SDI link0

assign cmp_gt_ctrl[0] = qpll0reset; //qpll0reset
assign cmp_gt_ctrl[1] = 1'b0; //qpll0pd
assign cmp_gt_ctrl[2] = qpll1reset; //qpll1reset
assign cmp_gt_ctrl[3] = 1'b0; //qpll1pd

assign cmp_gt_ctrl[6:4] = 3'b001; //qpll0refclksel;

assign cmp_gt_ctrl[7] = 1'b1; //qpll0refclksel_valid;

assign cmp_gt_ctrl[10:8] = 3'b001; //qpll1refclksel

assign cmp_gt_ctrl[11] = 1'b1; //qpll1refclksel_valid
//SDI link0
assign cmp_gt_ctrl[12] = ~fmc_init_done; //cpllreset
assign cmp_gt_ctrl[13] = 1'b0; //cpllpd
assign cmp_gt_ctrl[14] = si5324_stable_d2; //txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 0
assign cmp_gt_ctrl[15] = fmc_init_done_d2; //rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 0
assign cmp_gt_ctrl[18:16] = 3'b000; //cpll0 ref clk sel (unused in document)
assign cmp_gt_ctrl[19] = 1'b0; //cpllrefclksel0_valid (unused in document)
assign cmp_gt_ctrl[22:20] = 3'b000; //gt_loopback
//SDI link1
assign cmp_gt_ctrl[24] = ~fmc_init_done; //cpllreset
assign cmp_gt_ctrl[25] = 1'b0; //cpllpd

assign cmp_gt_ctrl[26] = 1'b1; //txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 1

assign cmp_gt_ctrl[27] = 1'b1; //rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 1
assign cmp_gt_ctrl[30:28] = 3'b000; //cpll0 ref clk sel (unused in document)
assign cmp_gt_ctrl[31] = 1'b0; //cpllrefclksel0_valid (unused in document)
assign cmp_gt_ctrl[34:32] = 3'b000; //gt_loopback

  

 

 

Regards

AYE

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1 Solution

Accepted Solutions
1,056 Views
Registered: ‎12-25-2018

Hi xud,

Try on the new UHD-SDI GT for SDI link1, is working now. Thanks for the patch.

 

Regards

AYE

View solution in original post

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4 Replies
1,142 Views
Registered: ‎12-25-2018

Hi guys,

Any one can help me?

I still have difficulty in getting SDI link 1 to work in UHD-SDI_GT core. SDI link 0 is always working. 

I am using Vivado 2018.3.

 

 

Regards

AYE

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

yan-eng.ang@leica-microsystems.com 

It's related to a known issue in UHD-SDI GT. Hopefully late next week the fix will be release as AR 72075.

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1,092 Views
Registered: ‎12-25-2018

Hi xud,

Thanks for informing. Otherwise I will spent more time troubleshooting SDI link 1 on UHD-SDI GT.

Will be waiting for the fix. Because I need to use 4 SDI link on one quad bank on ZCU102 board.

 

 

Regards

AYE

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1,057 Views
Registered: ‎12-25-2018

Hi xud,

Try on the new UHD-SDI GT for SDI link1, is working now. Thanks for the patch.

 

Regards

AYE

View solution in original post

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