cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
1,259 Views
Registered: ‎03-30-2019

Problem with Pixel clock on Video Timing Control for VGA

Hello,

I was successfully able to use the Video Test Pattern (TPG), Video Timing Control (VTC), and Axi Stream to Video out (VO) IPs to get a VGA output on a Zynq 7000 (Avnet minized).

The problem is that for VGA 640x480 @ 60 Hz, I had to set the clocking wizard to send 50 MHz to the VTC and VO. I would have expected that I need to send 25 Mhz, not 50.

In the block design GUI, VTC is set to 640x480p. TPG is also set to 640x480 (max).

On the PS side, I just set the TPG registers to enable the pattern.

I have attached the Block design and VTC settings and VGA output. Any idea why I am having to use double the pixel clock frequency?

Thanks!

 

Screenshot from 2019-07-24 17-36-46.png
IMG_20190724_173825.jpg
0 Kudos
14 Replies
Highlighted
Moderator
Moderator
1,218 Views
Registered: ‎11-09-2015

Hi @electronut 

You are right. The pixel clock for a 640x480p resolution should be 25.2MHz.

So why would you need to double the frequency.

I guess you might want to check the code inside your rgb2vga IP. It might be that it is sending the data in DDR (Double Data Rate). You might want to check the same if the monitor is not accepting DDR for the resolution.

Sometime, it is required to double the pixel clock (see my reply on this topic as reference)

On thing you might want to check is enable the menu in the monitor. The resolution detected should be printed. Check if it is 640*480@60Hz


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Visitor
Visitor
1,205 Views
Registered: ‎03-30-2019

Thanks for the reply. The topic link you posted seems broken. Could you check it?
0 Kudos
Highlighted
Moderator
Moderator
1,192 Views
Registered: ‎11-09-2015


@electronut wrote:
Thanks for the reply. The topic link you posted seems broken. Could you check it?

Fixed ;)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Visitor
Visitor
1,155 Views
Registered: ‎03-30-2019

Hello,

I've been able to get the test patterns working, but the double frequency is still a mystery. 

Here's a repo which shows my block diagram and PS/PL code:

https://github.com/electronut/learn-fpga/tree/master/zynq/video_ip_test

Regards

 

0 Kudos
Highlighted
Moderator
Moderator
1,149 Views
Registered: ‎11-09-2015

HI @electronut 

As mentioned the double frequency is probably required by your monitor


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Visitor
Visitor
1,146 Views
Registered: ‎03-30-2019

The monitor is not seeing the double frequency. hsync/vsycn signals are generated correctly only if I supply 50 MHz to VTC.

0 Kudos
Highlighted
Moderator
Moderator
1,142 Views
Registered: ‎11-09-2015

Hi @electronut 

Some monitors expect a double data rate, i.e. the pixel clock to be doubled for some resolutions. It will still mention it as the resolution you are trying to achieve.

Getting the details of the monitor might help


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Teacher
Teacher
1,124 Views
Registered: ‎06-16-2013

Hi @electronut 

 

According to your previous posted picture, your FPGA board connects to Monitor via analog RGB signal.

It doesn't require clock, only requires sync signals (hsync and vsync).

 

In this case, even if your logic use double clock, rising and falling clock, video signal is taken a sample by other sampling clock which is generated from hsync on ADC in Monitor.

 

So, you say "The monitor is not seeing the double frequency."

 

Best regards,

Highlighted
Visitor
Visitor
1,103 Views
Registered: ‎03-30-2019

Yes, as I had mentioned before, it's not the monitor, as the monitor sees the hsync and vsync signals at the expected frequencies for 640 x 480 @ 60 Hz.

The issue is that I am having to set 50 MHz (using clocking wizard) on the VTC to generate these hsync/vsync signals. I would have expected that I need to set 25 MHz. I am attaching the block design for your reference.

Regards

bd.png
0 Kudos
Highlighted
Teacher
Teacher
1,099 Views
Registered: ‎06-16-2013

Hi @electronut 

 

If you fix this issue, I suggest you to change the connection.

 

- vid_io_out_clk on AXI4Stream to Video out and clk on vga_out.

 

Because this clock is used pixel clock and if the output resolution is VGA@60Hz (640x480@60Hz), pixel clock is 25.175MHz which has tolerance of 0.5[%].

 

So, I suggest you to generate aboud 25[MHz] as pixel clock, too.

 

Best regards,

0 Kudos
Highlighted
Visitor
Visitor
1,090 Views
Registered: ‎03-30-2019

So, I suggest you to generate aboud 25[MHz] as pixel clock, too.

But I have already tried that. My original question was exactly about this. Sending 25 MHz as pixel clock results in hsync/vsync signals at half the expected frequency. I had to increase pixel clock to 50 Mhz to get the correct hsync/vsync signals. 

0 Kudos
Highlighted
Teacher
Teacher
1,085 Views
Registered: ‎06-16-2013

Hi @electronut 

 

Did you follow VESA video timing ?

If yes, I guess there is route cause in your RTL design.

 

Best regards,

0 Kudos
Highlighted
Explorer
Explorer
1,070 Views
Registered: ‎06-25-2014

First off, I have not used the VTG core so am no expert!

 

The only thing I can see (after a quick look) is more of a question.. What is the VTG_CE signal doing coming from the Video to stream block into the VTG? Perhaps this is causing the VTG to operate at half rate for some reason?

0 Kudos
Highlighted
Explorer
Explorer
1,064 Views
Registered: ‎06-25-2014

Also, if you find this signal is toggling when you have a look then I also notice figure 3.1 of pg044 only shows vtg_ce connected gen_clken, so maybe tie VTC's clken pin high. 

0 Kudos