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slymen
Newbie
Newbie
8,789 Views
Registered: ‎11-12-2008

Problem with the behaviour simulation of fft 91i CORE generator examples.

Hi,

 

I work under ISE 10.1.03(nt) ( free version downloaded from Xilinx) website.

 

I have downloaded the Fast Fourier Transform v4.1 (Radix 4) from

http://www.xilinx.com/support/software/coregen/91i_coregen_examples.htm

 

I open the project. ISE warn me that the project need to be upgrade to the new version 10.1.03.

 

Then, when i want to simulate the behavioral model "desig_top_tb - behaviour. vhd",

 

i have no error, some warnings 

WARNING: the property 'Use Time Based Reporting' was selected for the process 'Generate Power Data' in a previous version of ISE.

WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 12581. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 12582. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 4575. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 4647. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 4666. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100404. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100406. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100408. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100665. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100404. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100406. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100408. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100665. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100404. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100406. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100665. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "N:/K.39/rtf/vhdl/src/unisims/unisim_VITAL.vhd" Line 100688. Comparison between unequal length arrays always returns FALSE
WARNING:Simulator:784 - This is a limited version of the ISE Simulator(ISim).
 


and the chronogram(in attachment) shows that the output of the fft is equal to zero :

 

Do you have the same behavior ?

Did i miss a step ?

 

thank you.

 

 

chronogram-fft-simulation.JPG
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4 Replies
8,673 Views
Registered: ‎11-05-2008

I have the same problem with fft core V5, I get zeros at the output and don't know why, I almost tried alot of combinations for input but no thing worked.
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ywu
Xilinx Employee
Xilinx Employee
8,431 Views
Registered: ‎11-28-2007

You need to run the simulation for about 500us to get the valid output data (dv=1) (see sanpshot below) as it's a 8192 pt FFT. You may also want to look at the timing diagrams in the FFT user guide so you know what to expect in the waveform.

 

Cheers,

Jim

 

 

 

 

Cheers,
Jim
ScreenHunter_01 Jan. 15 11.00.gif
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alexgiul
Explorer
Explorer
8,023 Views
Registered: ‎02-18-2008

Hi slymen, I try the link you have posted but I cannot download any example.

 

Can you check? or can you send me a correct link? my email is alexgiul@hotmail.com

 

 

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chenhongyi123
Visitor
Visitor
7,017 Views
Registered: ‎01-05-2009

I also download  the   example, but now i can't find  it.

this link is invalid too, I think the examples isn't exist in Xilinx web!

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