cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chldlrtjd
Explorer
Explorer
218 Views
Registered: ‎06-03-2015

Question about VDMA transfer size in DisplayPort 1.4 RX Subsystem (DisplayPort example).

Jump to solution

Dear Xilinx experts.

Thank you very much for your support and kind answers.

I am studying DisplayPort 1.4 RX Subsystem (DisplayPort example).

My Vivado version is 2018.3. The device is xcky040-ffva1156-2-e.

I am porting the example into our design (using FPGA xcku115-flvf1924-2-i).

The DP RX data is tranfered to DDR4 via VDMA.


I have a question about VDMA transfer size setting in DisplayPort 1.4 RX Subsystem (DisplayPort example).

If the incoming video data (DP RX) has the following parameters, what is the VDMA transfer size?

H_ACTIVE = 2920, H_BACK = 40, H_FRONT = 20, H_SYNC = 20. Total = 3000.

V_ACTIVE = 1900, H_BACK = 100, H_FRONT = 40, H_SYNC = 40. Total = 2080.

The Pixel is 24 bit (3 byte) using 8 bit RGB.


In this case, which is correct VDMA transfer size?

#1) 2920 * 1900 * 3 byte = 16,644,000 byte.

#2) 3000 * 2080 * 3 byte = 18,720,000 byte.


I will appreciate if I can get the answer.

Thank you very much.

 

Ick-Sung Choi.

0 Kudos
1 Solution

Accepted Solutions
florentw
Moderator
Moderator
193 Views
Registered: ‎11-09-2015

Hi @chldlrtjd 

The AXI VDMA is connected through AXI4-Stream and the AXI4-Stream interface does not have any notion of blanking period.

Thus this is only the the active period which is transmitted through the AXI4-Stream and thus saved through the VDMA.

One thing to be cautious with the VDMA is that it it transmitting the full width of the AXI4-Stream data. So let say that the AXI4-Stream is 24-bit (i.e. 3 bytes) then if you have a 2920 * 1900 resolution the VDMA transfer will always be 2920 * 1900 * 3 byte independantly if you are transmitting RGB  8-bit(3 components per pixels) or YCbCr422 8-bit (2 components per pixels, i.e. only 2 bytes actively used)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

2 Replies
florentw
Moderator
Moderator
194 Views
Registered: ‎11-09-2015

Hi @chldlrtjd 

The AXI VDMA is connected through AXI4-Stream and the AXI4-Stream interface does not have any notion of blanking period.

Thus this is only the the active period which is transmitted through the AXI4-Stream and thus saved through the VDMA.

One thing to be cautious with the VDMA is that it it transmitting the full width of the AXI4-Stream data. So let say that the AXI4-Stream is 24-bit (i.e. 3 bytes) then if you have a 2920 * 1900 resolution the VDMA transfer will always be 2920 * 1900 * 3 byte independantly if you are transmitting RGB  8-bit(3 components per pixels) or YCbCr422 8-bit (2 components per pixels, i.e. only 2 bytes actively used)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

chldlrtjd
Explorer
Explorer
186 Views
Registered: ‎06-03-2015

Dear florentw.

Thank you very much for your precious answer.

 

 

 

0 Kudos