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Contributor
Contributor
656 Views
Registered: ‎08-28-2019

Reading frames loaded from SD Card with VDMA

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Hello, 

I loaded a frame (.bif)  from an SD card in  and tried reading with VDMA. I could not get any output so, I did some debugging and realized that, the the TREADY, ARREADY and RLAST are '1' and the remaining signals are '0'. What could be the issue? The Block design and the sample waveforms can be found below.

Thank you 

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Contributor
Contributor
539 Views
Registered: ‎08-28-2019

I finally sloved the problem. I connected the active low signals to GND instead of leaving the signals unconnected.  The frame was finally read.

Thank you

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Moderator
Moderator
595 Views
Registered: ‎11-09-2015

Hi @baring42read 

First question is: are you able to access the image on the SDcard if you read from the PS?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
584 Views
Registered: ‎08-28-2019
Hello,
Yes, I was able to access the SD card and read the data to a DDR. Initially, I was using Xil_Out to configure VDMA and must have missed something. So, I did it the drivers in the xaxivdma.h and read the data. But I am on able to display the frame with VGA though with ILA, I can see the data being read. Also, the VTC does not generate any signals and the vtg_ce that connects to gen_clk ls constant low. At this point, I have data till the Video in of AXI to Video Out IP. Also, I have connected the signals are required, the enables, and resets .
Any suggestions?
Thank you
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Moderator
Moderator
582 Views
Registered: ‎11-09-2015

Hi @baring42read 

Is the TVALID from VDMA to AXI4-Stream to Video Out HIGH?

If yes, you might have something wrong in the polarity of the enable or reset signals


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
558 Views
Registered: ‎08-28-2019

Yes, the TVALID is HIGH as shown on the waveform below. Also, I connected the resests and enable signals are expected but no output signals are generated by AXI to Video stream out and I suspect as a reseult of this, vtg_ce is constantly low and the VTC does not generate any signals. I don't know what could be wrong.Capture2.PNGCapture3.PNG

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Contributor
Contributor
540 Views
Registered: ‎08-28-2019

I finally sloved the problem. I connected the active low signals to GND instead of leaving the signals unconnected.  The frame was finally read.

Thank you

View solution in original post

Moderator
Moderator
493 Views
Registered: ‎11-09-2015

HI @baring42read 

As this is now solved for you, could you kindly mark a reply as accepted solution to close the thread?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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